radeonsi: enable TC-compatible stencil compression on VI
Most things are in place. Ideally we won't see decompress blits for stencil anymore. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -332,6 +332,8 @@ si_flush_depth_texture(struct si_context *sctx,
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}
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}
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assert(!tex->tc_compatible_htile || levels_z == 0);
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assert(!tex->tc_compatible_htile || levels_z == 0);
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assert(!tex->tc_compatible_htile || levels_s == 0 ||
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!r600_can_sample_zs(tex, true));
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/* We may have to allocate the flushed texture here when called from
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/* We may have to allocate the flushed texture here when called from
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* si_decompress_subresource.
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* si_decompress_subresource.
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@ -339,8 +339,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
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}
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}
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if (rtex->htile_buffer &&
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if (rtex->htile_buffer &&
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rtex->tc_compatible_htile &&
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rtex->tc_compatible_htile) {
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!is_stencil_sampler) {
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
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rtex->htile_buffer, usage,
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rtex->htile_buffer, usage,
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RADEON_PRIO_HTILE, check_mem);
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RADEON_PRIO_HTILE, check_mem);
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@ -424,7 +423,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
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if (sscreen->b.chip_class <= VI)
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if (sscreen->b.chip_class <= VI)
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meta_va += base_level_info->dcc_offset;
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meta_va += base_level_info->dcc_offset;
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} else if (tex->tc_compatible_htile && !is_stencil) {
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} else if (tex->tc_compatible_htile) {
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meta_va = tex->htile_buffer->gpu_address;
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meta_va = tex->htile_buffer->gpu_address;
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}
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}
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@ -571,7 +570,8 @@ static bool depth_needs_decompression(struct r600_texture *rtex,
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struct si_sampler_view *sview)
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struct si_sampler_view *sview)
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{
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{
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return rtex->db_compatible &&
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return rtex->db_compatible &&
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(!rtex->tc_compatible_htile || sview->is_stencil_sampler);
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(!rtex->tc_compatible_htile ||
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!r600_can_sample_zs(rtex, sview->is_stencil_sampler));
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}
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}
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static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
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static void si_update_compressed_tex_shader_mask(struct si_context *sctx,
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@ -1398,7 +1398,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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if (!rtex->tc_compatible_htile)
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if (!rtex->tc_compatible_htile)
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rtex->dirty_level_mask |= 1 << surf->u.tex.level;
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rtex->dirty_level_mask |= 1 << surf->u.tex.level;
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if (rtex->surface.flags & RADEON_SURF_SBUFFER)
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if (rtex->surface.flags & RADEON_SURF_SBUFFER &&
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(!rtex->tc_compatible_htile || !rtex->can_sample_s))
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rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
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rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
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}
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}
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if (sctx->framebuffer.compressed_cb_mask) {
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if (sctx->framebuffer.compressed_cb_mask) {
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