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radv: pass queue index into winsys submission 

This is so we can submit on separate queues if needed

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Dave Airlie 2016-12-01 01:14:49 +00:00 committed by Bas Nieuwenhuizen
parent d0e6fb0574
commit d270b5fac3
3 changed files with 13 additions and 5 deletions
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4
src/amd/vulkan/radv_device.c
View File

@ -855,7 +855,7 @@ VkResult radv_QueueSubmit(
if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
can_patch = false;
}
ret = queue->device->ws->cs_submit(ctx, cs_array,
ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array,
pSubmits[i].commandBufferCount,
can_patch, base_fence);
if (ret)
@ -865,7 +865,7 @@ VkResult radv_QueueSubmit(
if (fence) {
if (!submitCount)
ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, &queue->device->empty_cs,
1, false, base_fence);
fence->submitted = true;

1
src/amd/vulkan/radv_radeon_winsys.h
View File

@ -301,6 +301,7 @@ struct radeon_winsys {
void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
int (*cs_submit)(struct radeon_winsys_ctx *ctx,
int queue_index,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
bool can_patch,

13
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View File

@ -510,6 +510,7 @@ static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
}
static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
struct radeon_winsys_fence *_fence)
@ -550,6 +551,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
}
request.ip_type = cs0->hw_ip;
request.ring = queue_idx;
request.number_of_ibs = 1;
request.ibs = &cs0->ib;
request.resources = bo_list;
@ -574,6 +576,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
}
static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
struct radeon_winsys_fence *_fence)
@ -600,6 +603,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
}
request.ip_type = cs0->hw_ip;
request.ring = queue_idx;
request.resources = bo_list;
request.number_of_ibs = cnt;
request.ibs = ibs;
@ -639,6 +643,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
}
static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
struct radeon_winsys_fence *_fence)
@ -700,6 +705,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
ib.ib_mc_address = ws->buffer_get_va(bo);
request.ip_type = cs0->hw_ip;
request.ring = queue_idx;
request.resources = bo_list;
request.number_of_ibs = 1;
request.ibs = &ib;
@ -730,6 +736,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
}
static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
int queue_idx,
struct radeon_winsys_cs **cs_array,
unsigned cs_count,
bool can_patch,
@ -737,13 +744,13 @@ static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
if (!cs->ws->use_ib_bos) {
return radv_amdgpu_winsys_cs_submit_sysmem(_ctx, cs_array,
return radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, cs_array,
cs_count, _fence);
} else if (can_patch && cs_count > AMDGPU_CS_MAX_IBS_PER_SUBMIT && false) {
return radv_amdgpu_winsys_cs_submit_chained(_ctx, cs_array,
return radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, cs_array,
cs_count, _fence);
} else {
return radv_amdgpu_winsys_cs_submit_fallback(_ctx, cs_array,
return radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, cs_array,
cs_count, _fence);
}
}