freedreno/a6xx: Fix clip_mask
The clip_mask needs to also take into account rast->clip_plane_enable
Fixes: f2ae8d116a
("freedreno/a6xx: Implement user clip/cull distances")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14643>
This commit is contained in:
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5e2bd30ea4
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@ -87,6 +87,7 @@ fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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.key = {
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.key = {
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.rasterflat = ctx->rasterizer->flatshade,
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.rasterflat = ctx->rasterizer->flatshade,
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},
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},
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.clip_plane_enable = ctx->rasterizer->clip_plane_enable,
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},
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},
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.rasterflat = ctx->rasterizer->flatshade,
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.rasterflat = ctx->rasterizer->flatshade,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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@ -151,7 +151,8 @@ setup_state_map(struct fd_context *ctx)
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BIT(FD6_GROUP_ZSA));
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BIT(FD6_GROUP_ZSA));
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fd_context_add_map(ctx, FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG,
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fd_context_add_map(ctx, FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG,
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BIT(FD6_GROUP_LRZ) | BIT(FD6_GROUP_LRZ_BINNING));
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BIT(FD6_GROUP_LRZ) | BIT(FD6_GROUP_LRZ_BINNING));
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fd_context_add_map(ctx, FD_DIRTY_PROG, BIT(FD6_GROUP_PROG));
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fd_context_add_map(ctx, FD_DIRTY_PROG | FD_DIRTY_RASTERIZER_CLIP_PLANE_ENABLE,
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BIT(FD6_GROUP_PROG));
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fd_context_add_map(ctx, FD_DIRTY_RASTERIZER, BIT(FD6_GROUP_RASTERIZER));
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fd_context_add_map(ctx, FD_DIRTY_RASTERIZER, BIT(FD6_GROUP_RASTERIZER));
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fd_context_add_map(ctx,
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fd_context_add_map(ctx,
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FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD |
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FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD |
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@ -156,6 +156,7 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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.sample_shading = (ctx->min_samples > 1),
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.sample_shading = (ctx->min_samples > 1),
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.msaa = (ctx->framebuffer.samples > 1),
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.msaa = (ctx->framebuffer.samples > 1),
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},
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},
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.clip_plane_enable = ctx->rasterizer->clip_plane_enable,
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},
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},
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.rasterflat = ctx->rasterizer->flatshade,
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.rasterflat = ctx->rasterizer->flatshade,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
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@ -195,7 +196,7 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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ir3_fixup_shader_state(&ctx->base, &emit.key.key);
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ir3_fixup_shader_state(&ctx->base, &emit.key.key);
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if (!(ctx->dirty & FD_DIRTY_PROG)) {
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if (!(ctx->gen_dirty & BIT(FD6_GROUP_PROG))) {
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emit.prog = fd6_ctx->prog;
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emit.prog = fd6_ctx->prog;
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} else {
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} else {
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fd6_ctx->prog = fd6_emit_get_prog(&emit);
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fd6_ctx->prog = fd6_emit_get_prog(&emit);
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@ -585,6 +585,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
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cull_mask = last_shader->cull_mask;
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cull_mask = last_shader->cull_mask;
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uint8_t clip_cull_mask = clip_mask | cull_mask;
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uint8_t clip_cull_mask = clip_mask | cull_mask;
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clip_mask &= cache_key->clip_plane_enable;
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/* If we have streamout, link against the real FS, rather than the
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/* If we have streamout, link against the real FS, rather than the
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* dummy FS used for binning pass state, to ensure the OUTLOC's
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* dummy FS used for binning pass state, to ensure the OUTLOC's
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* match. Depending on whether we end up doing sysmem or gmem,
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* match. Depending on whether we end up doing sysmem or gmem,
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@ -27,6 +27,8 @@
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#ifndef IR3_CACHE_H_
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#ifndef IR3_CACHE_H_
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#define IR3_CACHE_H_
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#define IR3_CACHE_H_
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#include "pipe/p_state.h"
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#include "ir3/ir3_shader.h"
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#include "ir3/ir3_shader.h"
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/*
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/*
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@ -39,6 +41,11 @@
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struct ir3_cache_key {
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struct ir3_cache_key {
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struct ir3_shader_state *vs, *hs, *ds, *gs, *fs; // 5 pointers
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struct ir3_shader_state *vs, *hs, *ds, *gs, *fs; // 5 pointers
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struct ir3_shader_key key; // 7 dwords
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struct ir3_shader_key key; // 7 dwords
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/* Additional state that effects the cached program state, but
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* not the compiled shader:
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*/
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unsigned clip_plane_enable : PIPE_MAX_CLIP_PLANES;
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};
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};
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/* per-gen backend program state object should subclass this for it's
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/* per-gen backend program state object should subclass this for it's
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