ac/gpu_info: add has_sparse_vm_mappings
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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125adc92ad
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@ -330,6 +330,13 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
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info->has_indirect_compute_dispatch = true;
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/* SI doesn't support unaligned loads. */
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info->has_unaligned_shader_loads = info->chip_class != SI;
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/* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
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* these faults are mitigated in software.
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* Disable sparse mappings on GFX9 due to hangs.
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*/
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info->has_sparse_vm_mappings =
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info->chip_class >= CIK && info->chip_class <= VI &&
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info->drm_minor >= 13;
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info->num_render_backends = amdinfo->rb_pipes;
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/* The value returned by the kernel driver was wrong. */
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@ -488,6 +495,7 @@ void ac_print_gpu_info(struct radeon_info *info)
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printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
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printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
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printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
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printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
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printf("Shader core info:\n");
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printf(" max_shader_clock = %i\n", info->max_shader_clock);
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@ -107,6 +107,7 @@ struct radeon_info {
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bool kernel_flushes_tc_l2_after_ib;
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bool has_indirect_compute_dispatch;
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bool has_unaligned_shader_loads;
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bool has_sparse_vm_mappings;
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/* Shader cores. */
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uint32_t r600_max_quad_pipes; /* wave size / 16 */
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@ -229,17 +229,8 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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return !sscreen->info.has_unaligned_shader_loads;
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case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
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/* TODO: GFX9 hangs. */
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if (sscreen->info.chip_class >= GFX9)
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return 0;
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/* Disable on SI due to VM faults in CP DMA. Enable once these
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* faults are mitigated in software.
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*/
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if (sscreen->info.chip_class >= CIK &&
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sscreen->info.drm_major == 3 &&
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sscreen->info.drm_minor >= 13)
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return RADEON_SPARSE_PAGE_SIZE;
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return 0;
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return sscreen->info.has_sparse_vm_mappings ?
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RADEON_SPARSE_PAGE_SIZE : 0;
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case PIPE_CAP_PACKED_UNIFORMS:
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if (sscreen->debug_flags & DBG(NIR))
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@ -547,6 +547,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
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/* SI doesn't support unaligned loads. */
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ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
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ws->info.drm_minor >= 50;
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ws->info.has_sparse_vm_mappings = false;
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ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
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