KonstantinSeurer
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support branch and loop in pixel shader 

most of the sample working with some small modification
This commit is contained in:
Zou Nan hai 2007-06-21 10:22:28 +08:00
parent 58eac1bbf3
commit d19d0596da
17 changed files with 1363 additions and 110 deletions
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6
progs/glsl/CH06-brick.frag.txt
View File

@ -23,7 +23,11 @@ void main()
position = MCposition / BrickSize;
if (fract(position.y * 0.5) > 0.5)
// if (fract(position.y * 0.5) > 0.5)
// position.x += 0.5;
float tmp;
tmp = fract(position.y * 0.5);
if (tmp > 0.5)
position.x += 0.5;
position = fract(position);

2
progs/glsl/CH11-bumpmap.frag.txt
View File

@ -33,7 +33,7 @@ void main()
litColor = SurfaceColor * max(dot(normDelta, LightDir), 0.0);
vec3 reflectDir = reflect(LightDir, normDelta);
float spec = max(dot(EyeDir, reflectDir), 0.0);
float spec = max(dot(normalize(EyeDir), reflectDir), 0.0);
spec *= SpecularFactor;
litColor = min(litColor + spec, vec3(1.0));

9
progs/glsl/CH11-bumpmap.vert.txt
View File

@ -31,8 +31,9 @@ void main()
v.z = dot(LightPosition, n);
LightDir = normalize(v);
v.x = dot(EyeDir, t);
v.y = dot(EyeDir, b);
v.z = dot(EyeDir, n);
EyeDir = normalize(v);
/* v.x = dot(EyeDir, t);
v.y = dot(EyeDir, b);
v.z = dot(EyeDir, n);
EyeDir = normalize(EyeDir);
*/
}

7
progs/glsl/CH11-toyball.frag.txt
View File

@ -49,14 +49,15 @@ void main()
inorout += dot(distance, vec4(1.0));
distance.x = dot(p, HalfSpace4);
distance.y = StripeWidth - abs(p.z);
// distance.y = StripeWidth - abs(p.z);
distance.y = StripeWidth - abs(p.y);
distance = smoothstep(-FWidth, FWidth, distance);
inorout += distance.x;
inorout = clamp(inorout, 0.0, 1.0);
surfColor = mix(Yellow, Red, inorout);
surfColor = mix(surfColor, Blue, distance.y);
surfColor = mix(Yellow, Blue, distance.y);
surfColor = mix(surfColor, Red, inorout);
// normal = point on surface for sphere at (0,0,0)
normal = p;

7
progs/glsl/CH11-toyball.vert.txt
View File

@ -14,10 +14,11 @@ uniform vec4 BallCenter; // ball center in modelling coordinates
void main()
{
//orig: ECposition = gl_ModelViewMatrix * gl_Vertex;
ECposition = gl_ModelViewMatrix * gl_Vertex;
ECposition = gl_TextureMatrix[0] * gl_Vertex;
ECposition = gl_ModelViewMatrix * ECposition;
// ECposition = gl_TextureMatrix[0] * gl_Vertex;
// ECposition = gl_MultiTexCoord0 * gl_Vertex;
// ECposition = gl_ModelViewMatrix * ECposition;
ECballCenter = gl_ModelViewMatrix * BallCenter;
gl_Position = ftransform();

1
src/mesa/drivers/dri/i965/Makefile
View File

@ -70,6 +70,7 @@ DRIVER_SOURCES = \
brw_wm_emit.c \
brw_wm_fp.c \
brw_wm_iz.c \
brw_wm_glsl.c \
brw_wm_pass0.c \
brw_wm_pass1.c \
brw_wm_pass2.c \

8
src/mesa/drivers/dri/i965/brw_eu.h
View File

@ -668,7 +668,10 @@ static __inline struct brw_indirect brw_indirect( GLuint addr_subnr, GLint offse
return ptr;
}
static __inline struct brw_instruction *current_insn( struct brw_compile *p)
{
return &p->store[p->nr_insn];
}
void brw_pop_insn_state( struct brw_compile *p );
void brw_push_insn_state( struct brw_compile *p );
@ -808,9 +811,10 @@ void brw_ENDIF(struct brw_compile *p,
struct brw_instruction *brw_DO(struct brw_compile *p,
GLuint execute_size);
void brw_WHILE(struct brw_compile *p,
struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *patch_insn);
struct brw_instruction *brw_BREAK(struct brw_compile *p);
/* Forward jumps:
*/
void brw_land_fwd_jump(struct brw_compile *p,

28
src/mesa/drivers/dri/i965/brw_eu_emit.c
View File

@ -186,7 +186,7 @@ void brw_set_src1( struct brw_instruction *insn,
* in the future:
*/
assert (reg.address_mode == BRW_ADDRESS_DIRECT);
assert (reg.file == BRW_GENERAL_REGISTER_FILE);
//assert (reg.file == BRW_GENERAL_REGISTER_FILE);
if (insn->header.access_mode == BRW_ALIGN_1) {
insn->bits3.da1.src1_subreg_nr = reg.subnr;
@ -597,6 +597,20 @@ void brw_ENDIF(struct brw_compile *p,
}
}
struct brw_instruction *brw_BREAK(struct brw_compile *p)
{
struct brw_instruction *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
insn->header.mask_control = BRW_MASK_DISABLE;
insn->bits3.if_else.pad0 = 0;
return insn;
}
/* DO/WHILE loop:
*/
struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
@ -608,13 +622,15 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
/* Override the defaults for this instruction:
*/
brw_set_dest(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(insn, retype(brw_vec1_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_dest(insn, brw_null_reg());
brw_set_src0(insn, brw_null_reg());
brw_set_src1(insn, brw_null_reg());
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = execute_size;
insn->header.predicate_control = BRW_PREDICATE_NONE;
/* insn->header.mask_control = BRW_MASK_ENABLE; */
insn->header.mask_control = BRW_MASK_DISABLE;
return insn;
}
@ -622,7 +638,7 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
void brw_WHILE(struct brw_compile *p,
struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *do_insn)
{
struct brw_instruction *insn;
@ -653,7 +669,9 @@ void brw_WHILE(struct brw_compile *p,
/* insn->header.mask_control = BRW_MASK_ENABLE; */
insn->header.mask_control = BRW_MASK_DISABLE;
p->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}

5
src/mesa/drivers/dri/i965/brw_vs.h
View File

@ -69,6 +69,11 @@ struct brw_vs_compile {
struct brw_reg tmp;
struct brw_reg stack;
struct {
GLboolean used_in_src;
struct brw_reg reg;
} output_regs[128];
struct brw_reg userplane[6];
};

84
src/mesa/drivers/dri/i965/brw_vs_emit.c
View File

@ -135,6 +135,13 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
reg++;
}
for (i = 0; i < 128; i++) {
if (c->output_regs[i].used_in_src) {
c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
reg++;
}
}
c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg, 0);
reg += 2;
@ -686,28 +693,28 @@ static void emit_arl( struct brw_vs_compile *c,
* account.
*/
static struct brw_reg get_arg( struct brw_vs_compile *c,
struct prog_src_register src )
struct prog_src_register *src )
{
struct brw_reg reg;
if (src.File == PROGRAM_UNDEFINED)
if (src->File == PROGRAM_UNDEFINED)
return brw_null_reg();
if (src.RelAddr)
reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src.Index);
if (src->RelAddr)
reg = deref(c, c->regs[PROGRAM_STATE_VAR][0], src->Index);
else
reg = get_reg(c, src.File, src.Index);
reg = get_reg(c, src->File, src->Index);
/* Convert 3-bit swizzle to 2-bit.
*/
reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src.Swizzle, 0),
GET_SWZ(src.Swizzle, 1),
GET_SWZ(src.Swizzle, 2),
GET_SWZ(src.Swizzle, 3));
reg.dw1.bits.swizzle = BRW_SWIZZLE4(GET_SWZ(src->Swizzle, 0),
GET_SWZ(src->Swizzle, 1),
GET_SWZ(src->Swizzle, 2),
GET_SWZ(src->Swizzle, 3));
/* Note this is ok for non-swizzle instructions:
*/
reg.negate = src.NegateBase ? 1 : 0;
reg.negate = src->NegateBase ? 1 : 0;
return reg;
}
@ -921,10 +928,8 @@ post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst )
inst1 = &c->vp->program.Base.Instructions[insn];
brw_inst1 = inst1->Data;
switch (inst1->Opcode) {
case OPCODE_BRA:
case OPCODE_BRK:
case OPCODE_CAL:
case OPCODE_ENDLOOP:
case OPCODE_BRA:
target_insn = inst1->BranchTarget;
inst2 = &c->vp->program.Base.Instructions[target_insn];
brw_inst2 = inst2->Data;
@ -945,12 +950,12 @@ post_vs_emit( struct brw_vs_compile *c, struct brw_instruction *end_inst )
*/
void brw_vs_emit(struct brw_vs_compile *c )
{
#define MAX_IF_DEPTH 32
#define MAX_IFSN 32
struct brw_compile *p = &c->func;
GLuint nr_insns = c->vp->program.Base.NumInstructions;
GLuint insn, if_insn = 0;
struct brw_instruction *end_inst;
struct brw_instruction *if_inst[MAX_IF_DEPTH];
struct brw_instruction *if_inst[MAX_IFSN];
struct brw_indirect stack_index = brw_indirect(0, 0);
if (INTEL_DEBUG & DEBUG_VS) {
@ -962,6 +967,20 @@ void brw_vs_emit(struct brw_vs_compile *c )
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_access_mode(p, BRW_ALIGN_16);
/* Message registers can't be read, so copy the output into GRF register
if they are used in source registers */
for (insn = 0; insn < nr_insns; insn++) {
GLuint i;
struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn];
for (i = 0; i < 3; i++) {
struct prog_src_register *src = &inst->SrcReg[i];
GLuint index = src->Index;
GLuint file = src->File;
if (file == PROGRAM_OUTPUT && index != VERT_RESULT_HPOS)
c->output_regs[index].used_in_src = GL_TRUE;
}
}
/* Static register allocation
*/
brw_vs_alloc_regs(c);
@ -977,8 +996,15 @@ void brw_vs_emit(struct brw_vs_compile *c )
*/
inst->Data = &p->store[p->nr_insn];
if (inst->Opcode != OPCODE_SWZ)
for (i = 0; i < 3; i++)
args[i] = get_arg(c, inst->SrcReg[i]);
for (i = 0; i < 3; i++) {
struct prog_src_register *src = &inst->SrcReg[i];
GLuint index = src->Index;
GLuint file = src->File;
if (file == PROGRAM_OUTPUT&&c->output_regs[index].used_in_src)
args[i] = c->output_regs[index].reg;
else
args[i] = get_arg(c, src);
}
/* Get dest regs. Note that it is possible for a reg to be both
* dst and arg, given the static allocation of registers. So
@ -1085,13 +1111,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
case OPCODE_XPD:
emit_xpd(p, dst, args[0], args[1]);
break;
case OPCODE_INT:
/* XXX TODO track type information in shader program */
brw_MOV(p, dst, args[0]);
break;
case OPCODE_IF:
assert(if_insn < MAX_IF_DEPTH);
assert(if_insn < MAX_IFSN);
if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
break;
case OPCODE_ELSE:
@ -1101,6 +1122,11 @@ void brw_vs_emit(struct brw_vs_compile *c )
assert(if_insn > 0);
brw_ENDIF(p, if_inst[--if_insn]);
break;
case OPCODE_BRA:
brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
brw_set_predicate_control_flag_value(p, 0xff);
break;
case OPCODE_CAL:
brw_set_access_mode(p, BRW_ALIGN_1);
brw_ADD(p, deref_1uw(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
@ -1116,13 +1142,9 @@ void brw_vs_emit(struct brw_vs_compile *c )
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, brw_ip_reg(), deref_1uw(stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
case OPCODE_ENDLOOP:
case OPCODE_BRK:
case OPCODE_BRA:
case OPCODE_END:
brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
break;
case OPCODE_BGNLOOP:
case OPCODE_PRINT:
case OPCODE_BGNSUB:
case OPCODE_ENDSUB:
@ -1131,8 +1153,12 @@ void brw_vs_emit(struct brw_vs_compile *c )
_mesa_printf("Unsupport opcode %d in vertex shader\n", inst->Opcode);
break;
}
brw_set_predicate_control(p,
inst->CondUpdate?BRW_PREDICATE_NORMAL:BRW_PREDICATE_NONE);
if (inst->DstReg.File == PROGRAM_OUTPUT
&&inst->DstReg.Index != VERT_RESULT_HPOS
&&c->output_regs[inst->DstReg.Index].used_in_src)
brw_MOV(p, get_dst(c, inst->DstReg), dst);
release_tmps(c);
}

80
src/mesa/drivers/dri/i965/brw_wm.c
View File

@ -154,47 +154,49 @@ static void do_wm_prog( struct brw_context *brw,
c->fp = fp;
c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
/* Augment fragment program. Add instructions for pre- and
* post-fragment-program tasks such as interpolation and fogging.
*/
brw_wm_pass_fp(c);
/* Translate to intermediate representation. Build register usage
* chains.
*/
brw_wm_pass0(c);
/* Dead code removal.
*/
brw_wm_pass1(c);
/* Hal optimization
*/
brw_wm_pass_hal (c);
/* Register allocation.
*/
c->grf_limit = BRW_WM_MAX_GRF/2;
/* This is where we start emitting gen4 code:
*/
brw_init_compile(&c->func);
brw_wm_pass2(c);
c->prog_data.total_grf = c->max_wm_grf;
if (c->last_scratch) {
c->prog_data.total_scratch =
c->last_scratch + 0x40;
if (brw_wm_is_glsl(&c->fp->program)) {
brw_wm_glsl_emit(c);
} else {
c->prog_data.total_scratch = 0;
/* Augment fragment program. Add instructions for pre- and
* post-fragment-program tasks such as interpolation and fogging.
*/
brw_wm_pass_fp(c);
/* Translate to intermediate representation. Build register usage
* chains.
*/
brw_wm_pass0(c);
/* Dead code removal.
*/
brw_wm_pass1(c);
/* Hal optimization
*/
brw_wm_pass_hal (c);
/* Register allocation.
*/
c->grf_limit = BRW_WM_MAX_GRF/2;
/* This is where we start emitting gen4 code:
*/
brw_init_compile(&c->func);
brw_wm_pass2(c);
c->prog_data.total_grf = c->max_wm_grf;
if (c->last_scratch) {
c->prog_data.total_scratch =
c->last_scratch + 0x40;
} else {
c->prog_data.total_scratch = 0;
}
/* Emit GEN4 code.
*/
brw_wm_emit(c);
}
/* Emit GEN4 code.
*/
brw_wm_emit(c);
/* get the program
*/
program = brw_get_program(&c->func, &program_size);

10
src/mesa/drivers/dri/i965/brw_wm.h
View File

@ -231,6 +231,14 @@ struct brw_wm_compile {
GLuint grf_limit;
GLuint max_wm_grf;
GLuint last_scratch;
struct {
GLboolean inited;
struct brw_reg reg;
} wm_regs[PROGRAM_PAYLOAD+1][256][4];
struct brw_reg ret_reg;
GLuint reg_index;
GLuint tmp_index;
};
@ -259,4 +267,6 @@ void brw_wm_lookup_iz( GLuint line_aa,
GLuint lookup,
struct brw_wm_prog_key *key );
GLboolean brw_wm_is_glsl(struct gl_fragment_program *fp);
void brw_wm_glsl_emit(struct brw_wm_compile *c);
#endif

24
src/mesa/drivers/dri/i965/brw_wm_emit.c
View File

@ -229,20 +229,20 @@ static void emit_cinterp( struct brw_compile *p,
GLuint mask,
const struct brw_reg *arg0 )
{
struct brw_reg interp[4];
GLuint nr = arg0[0].nr;
GLuint i;
struct brw_reg interp[4];
GLuint nr = arg0[0].nr;
GLuint i;
interp[0] = brw_vec1_grf(nr, 0);
interp[1] = brw_vec1_grf(nr, 4);
interp[2] = brw_vec1_grf(nr+1, 0);
interp[3] = brw_vec1_grf(nr+1, 4);
interp[0] = brw_vec1_grf(nr, 0);
interp[1] = brw_vec1_grf(nr, 4);
interp[2] = brw_vec1_grf(nr+1, 0);
interp[3] = brw_vec1_grf(nr+1, 4);
for(i = 0; i < 4; i++ ) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */
}
}
for(i = 0; i < 4; i++ ) {
if (mask & (1<<i)) {
brw_MOV(p, dst[i], suboffset(interp[i],3)); /* TODO: optimize away like other moves */
}
}
}

16
src/mesa/drivers/dri/i965/brw_wm_fp.c
View File

@ -176,6 +176,7 @@ static struct prog_instruction *emit_insn(struct brw_wm_compile *c,
{
struct prog_instruction *inst = get_fp_inst(c);
*inst = *inst0;
inst->Data = (void *)inst0;
return inst;
}
@ -201,7 +202,6 @@ static struct prog_instruction * emit_op(struct brw_wm_compile *c,
inst->SrcReg[0] = src0;
inst->SrcReg[1] = src1;
inst->SrcReg[2] = src2;
return inst;
}
@ -907,8 +907,10 @@ void brw_wm_pass_fp( struct brw_wm_compile *c )
*/
out->DstReg.WriteMask = 0;
break;
case OPCODE_END:
emit_fog(c);
emit_fb_write(c);
break;
case OPCODE_PRINT:
break;
@ -917,15 +919,11 @@ void brw_wm_pass_fp( struct brw_wm_compile *c )
break;
}
}
emit_fog(c);
emit_fb_write(c);
if (INTEL_DEBUG & DEBUG_WM) {
_mesa_printf("\n\n\npass_fp:\n");
print_insns( c->prog_instructions, c->nr_fp_insns );
_mesa_printf("\n");
_mesa_printf("\n\n\npass_fp:\n");
print_insns( c->prog_instructions, c->nr_fp_insns );
_mesa_printf("\n");
}
}

1177
src/mesa/drivers/dri/i965/brw_wm_glsl.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
src/mesa/drivers/dri/i965/brw_wm_pass2.c
View File

@ -328,7 +328,7 @@ void brw_wm_pass2( struct brw_wm_compile *c )
c->state = PASS2_DONE;
if (INTEL_DEBUG & DEBUG_WM) {
brw_wm_print_program(c, "pass2/done");
brw_wm_print_program(c, "pass2/done");
}
}

7
src/mesa/drivers/dri/i965/brw_wm_state.c
View File

@ -34,6 +34,7 @@
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_wm.h"
#include "bufmgr.h"
/***********************************************************************
@ -134,9 +135,13 @@ static void upload_wm_unit(struct brw_context *brw )
if (fp->UsesKill ||
brw->attribs.Color->AlphaEnabled)
wm.wm5.program_uses_killpixel = 1;
if (brw_wm_is_glsl(fp))
wm.wm5.enable_8_pix = 1;
else
wm.wm5.enable_16_pix = 1;
}
wm.wm5.enable_16_pix = 1;
wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */
wm.wm5.legacy_line_rast = 0;
wm.wm5.legacy_global_depth_bias = 0;