radeonsi: move si_descriptors into a per-context array
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
parent
a29c4f9ebd
commit
d152c73712
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@ -263,6 +263,19 @@ si_descriptors_begin_new_cs(struct si_context *sctx, struct si_descriptors *desc
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/* SAMPLER VIEWS */
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static unsigned
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si_sampler_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_SAMPLERS;
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}
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static struct si_descriptors *
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si_sampler_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_sampler_descriptors_idx(shader)];
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}
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static void si_release_sampler_views(struct si_sampler_views *views)
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{
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int i;
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@ -270,7 +283,6 @@ static void si_release_sampler_views(struct si_sampler_views *views)
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for (i = 0; i < ARRAY_SIZE(views->views); i++) {
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pipe_sampler_view_reference(&views->views[i], NULL);
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}
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si_release_descriptors(&views->desc);
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}
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static void si_sampler_view_add_buffer(struct si_context *sctx,
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@ -298,8 +310,6 @@ static void si_sampler_views_begin_new_cs(struct si_context *sctx,
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si_sampler_view_add_buffer(sctx, views->views[i]->texture,
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RADEON_USAGE_READ);
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}
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si_descriptors_begin_new_cs(sctx, &views->desc);
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}
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void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
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@ -336,7 +346,7 @@ static void si_set_sampler_view(struct si_context *sctx,
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{
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_sampler_view *rview = (struct si_sampler_view*)view;
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struct si_descriptors *descs = &views->desc;
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struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
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if (views->views[slot] == view && !disallow_early_out)
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return;
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@ -468,6 +478,19 @@ si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
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/* IMAGE VIEWS */
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static unsigned
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si_image_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_IMAGES;
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}
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static struct si_descriptors*
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si_image_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_image_descriptors_idx(shader)];
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}
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static void
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si_release_image_views(struct si_images_info *images)
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{
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@ -478,8 +501,6 @@ si_release_image_views(struct si_images_info *images)
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pipe_resource_reference(&view->resource, NULL);
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}
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si_release_descriptors(&images->desc);
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}
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static void
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@ -497,8 +518,6 @@ si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *imag
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si_sampler_view_add_buffer(sctx, view->resource,
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RADEON_USAGE_READWRITE);
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}
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si_descriptors_begin_new_cs(sctx, &images->desc);
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}
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static void
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@ -507,7 +526,7 @@ si_disable_shader_image(struct si_context *ctx, unsigned shader, unsigned slot)
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struct si_images_info *images = &ctx->images[shader];
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if (images->enabled_mask & (1u << slot)) {
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struct si_descriptors *descs = &images->desc;
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struct si_descriptors *descs = si_image_descriptors(ctx, shader);
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pipe_resource_reference(&images->views[slot].resource, NULL);
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images->compressed_colortex_mask &= ~(1 << slot);
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@ -541,7 +560,7 @@ static void si_set_shader_image(struct si_context *ctx,
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{
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struct si_screen *screen = ctx->screen;
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struct si_images_info *images = &ctx->images[shader];
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struct si_descriptors *descs = &images->desc;
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struct si_descriptors *descs = si_image_descriptors(ctx, shader);
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struct r600_resource *res;
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if (!view || !view->resource) {
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@ -677,7 +696,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_textures_info *samplers = &sctx->samplers[shader];
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struct si_descriptors *desc = &samplers->views.desc;
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struct si_descriptors *desc = si_sampler_descriptors(sctx, shader);
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struct si_sampler_state **sstates = (struct si_sampler_state**)states;
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int i;
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@ -710,6 +729,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
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/* BUFFER RESOURCES */
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static void si_init_buffer_resources(struct si_buffer_resources *buffers,
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struct si_descriptors *descs,
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unsigned num_buffers,
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unsigned shader_userdata_index,
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enum radeon_bo_usage shader_usage,
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@ -720,20 +740,20 @@ static void si_init_buffer_resources(struct si_buffer_resources *buffers,
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buffers->priority = priority;
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buffers->buffers = CALLOC(num_buffers, sizeof(struct pipe_resource*));
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si_init_descriptors(&buffers->desc, shader_userdata_index, 4,
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si_init_descriptors(descs, shader_userdata_index, 4,
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num_buffers, NULL, ce_offset);
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}
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static void si_release_buffer_resources(struct si_buffer_resources *buffers)
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static void si_release_buffer_resources(struct si_buffer_resources *buffers,
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struct si_descriptors *descs)
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{
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int i;
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for (i = 0; i < buffers->desc.num_elements; i++) {
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for (i = 0; i < descs->num_elements; i++) {
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pipe_resource_reference(&buffers->buffers[i], NULL);
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}
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FREE(buffers->buffers);
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si_release_descriptors(&buffers->desc);
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}
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static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
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@ -749,8 +769,6 @@ static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
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(struct r600_resource*)buffers->buffers[i],
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buffers->shader_usage, buffers->priority);
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}
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si_descriptors_begin_new_cs(sctx, &buffers->desc);
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}
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/* VERTEX BUFFERS */
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@ -867,6 +885,19 @@ static bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
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/* CONSTANT BUFFERS */
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static unsigned
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si_const_buffer_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_CONST_BUFFERS;
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}
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static struct si_descriptors *
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si_const_buffer_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_const_buffer_descriptors_idx(shader)];
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}
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void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
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const uint8_t *ptr, unsigned size, uint32_t *const_offset)
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{
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@ -880,9 +911,10 @@ void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuf
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static void si_set_constant_buffer(struct si_context *sctx,
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struct si_buffer_resources *buffers,
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unsigned descriptors_idx,
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uint slot, struct pipe_constant_buffer *input)
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{
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struct si_descriptors *descs = &buffers->desc;
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struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
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assert(slot < descs->num_elements);
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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@ -905,7 +937,7 @@ static void si_set_constant_buffer(struct si_context *sctx,
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input->buffer_size, &buffer_offset);
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if (!buffer) {
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/* Just unbind on failure. */
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si_set_constant_buffer(sctx, buffers, slot, NULL);
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si_set_constant_buffer(sctx, buffers, descriptors_idx, slot, NULL);
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return;
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}
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va = r600_resource(buffer)->gpu_address + buffer_offset;
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@ -944,7 +976,8 @@ static void si_set_constant_buffer(struct si_context *sctx,
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void si_set_rw_buffer(struct si_context *sctx,
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uint slot, struct pipe_constant_buffer *input)
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{
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si_set_constant_buffer(sctx, &sctx->rw_buffers, slot, input);
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si_set_constant_buffer(sctx, &sctx->rw_buffers,
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SI_DESCS_RW_BUFFERS, slot, input);
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}
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static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
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@ -956,18 +989,33 @@ static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
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if (shader >= SI_NUM_SHADERS)
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return;
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si_set_constant_buffer(sctx, &sctx->const_buffers[shader], slot, input);
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si_set_constant_buffer(sctx, &sctx->const_buffers[shader],
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si_const_buffer_descriptors_idx(shader),
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slot, input);
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}
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/* SHADER BUFFERS */
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static unsigned
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si_shader_buffer_descriptors_idx(unsigned shader)
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{
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return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS +
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SI_SHADER_DESCS_SHADER_BUFFERS;
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}
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static struct si_descriptors *
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si_shader_buffer_descriptors(struct si_context *sctx, unsigned shader)
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{
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return &sctx->descriptors[si_shader_buffer_descriptors_idx(shader)];
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}
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static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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unsigned start_slot, unsigned count,
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struct pipe_shader_buffer *sbuffers)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->shader_buffers[shader];
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struct si_descriptors *descs = &buffers->desc;
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struct si_descriptors *descs = si_shader_buffer_descriptors(sctx, shader);
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unsigned i;
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assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
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@ -1019,7 +1067,7 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &buffers->desc;
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struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
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/* The stride field in the resource descriptor has 14 bits */
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assert(stride < (1 << 14));
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@ -1111,7 +1159,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &buffers->desc;
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struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
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unsigned old_num_targets = sctx->b.streamout.num_targets;
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unsigned i, bufidx;
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@ -1268,10 +1316,11 @@ void si_update_compressed_colortex_masks(struct si_context *sctx)
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/** Reset descriptors of buffer resources after \p buf has been invalidated. */
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static void si_reset_buffer_resources(struct si_context *sctx,
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struct si_buffer_resources *buffers,
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unsigned descriptors_idx,
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struct pipe_resource *buf,
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uint64_t old_va)
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{
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struct si_descriptors *descs = &buffers->desc;
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struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
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unsigned mask = buffers->enabled_mask;
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while (mask) {
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@ -1335,7 +1384,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Streamout buffers. (other internal buffers can't be invalidated) */
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for (i = SI_VS_STREAMOUT_BUF0; i <= SI_VS_STREAMOUT_BUF3; i++) {
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &buffers->desc;
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struct si_descriptors *descs =
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&sctx->descriptors[SI_DESCS_RW_BUFFERS];
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if (buffers->buffers[i] != buf)
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continue;
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@ -1359,8 +1409,10 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Constant and shader buffers. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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si_reset_buffer_resources(sctx, &sctx->const_buffers[shader],
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si_const_buffer_descriptors_idx(shader),
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buf, old_va);
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si_reset_buffer_resources(sctx, &sctx->shader_buffers[shader],
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si_shader_buffer_descriptors_idx(shader),
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buf, old_va);
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}
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@ -1373,7 +1425,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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struct si_descriptors *descs = &views->desc;
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struct si_descriptors *descs =
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si_sampler_descriptors(sctx, shader);
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unsigned mask = views->enabled_mask;
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while (mask) {
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@ -1395,7 +1448,8 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Shader images */
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images_info *images = &sctx->images[shader];
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struct si_descriptors *descs = &images->desc;
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struct si_descriptors *descs =
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si_image_descriptors(sctx, shader);
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unsigned mask = images->enabled_mask;
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while (mask) {
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@ -1464,10 +1518,11 @@ void si_update_all_texture_descriptors(struct si_context *sctx)
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static void si_mark_shader_pointers_dirty(struct si_context *sctx,
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unsigned shader)
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{
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sctx->const_buffers[shader].desc.pointer_dirty = true;
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sctx->shader_buffers[shader].desc.pointer_dirty = true;
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sctx->samplers[shader].views.desc.pointer_dirty = true;
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sctx->images[shader].desc.pointer_dirty = true;
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struct si_descriptors *descs =
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&sctx->descriptors[SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS];
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for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
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descs->pointer_dirty = true;
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if (shader == PIPE_SHADER_VERTEX)
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sctx->vertex_buffers.pointer_dirty = true;
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@ -1482,7 +1537,7 @@ static void si_shader_userdata_begin_new_cs(struct si_context *sctx)
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for (i = 0; i < SI_NUM_SHADERS; i++) {
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si_mark_shader_pointers_dirty(sctx, i);
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}
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sctx->rw_buffers.desc.pointer_dirty = true;
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sctx->descriptors[SI_DESCS_RW_BUFFERS].pointer_dirty = true;
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}
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/* Set a base register address for user data constants in the given shader.
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@ -1557,33 +1612,37 @@ static void si_emit_shader_pointer(struct si_context *sctx,
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void si_emit_graphics_shader_userdata(struct si_context *sctx,
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struct r600_atom *atom)
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{
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unsigned i;
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unsigned shader;
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uint32_t *sh_base = sctx->shader_userdata.sh_base;
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struct si_descriptors *descs;
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if (sctx->rw_buffers.desc.pointer_dirty) {
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si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
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descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
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if (descs->pointer_dirty) {
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si_emit_shader_pointer(sctx, descs,
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R_00B030_SPI_SHADER_USER_DATA_PS_0, true);
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si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
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si_emit_shader_pointer(sctx, descs,
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R_00B130_SPI_SHADER_USER_DATA_VS_0, true);
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si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
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si_emit_shader_pointer(sctx, descs,
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R_00B230_SPI_SHADER_USER_DATA_GS_0, true);
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si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
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si_emit_shader_pointer(sctx, descs,
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R_00B330_SPI_SHADER_USER_DATA_ES_0, true);
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si_emit_shader_pointer(sctx, &sctx->rw_buffers.desc,
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si_emit_shader_pointer(sctx, descs,
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R_00B430_SPI_SHADER_USER_DATA_HS_0, true);
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sctx->rw_buffers.desc.pointer_dirty = false;
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descs->pointer_dirty = false;
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}
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for (i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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unsigned base = sh_base[i];
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descs = &sctx->descriptors[SI_DESCS_FIRST_SHADER];
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for (shader = 0; shader < SI_NUM_GRAPHICS_SHADERS; shader++) {
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unsigned base = sh_base[shader];
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unsigned i;
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if (!base)
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continue;
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si_emit_shader_pointer(sctx, &sctx->const_buffers[i].desc, base, false);
|
||||
si_emit_shader_pointer(sctx, &sctx->shader_buffers[i].desc, base, false);
|
||||
si_emit_shader_pointer(sctx, &sctx->samplers[i].views.desc, base, false);
|
||||
si_emit_shader_pointer(sctx, &sctx->images[i].desc, base, false);
|
||||
for (i = 0; i < SI_NUM_SHADER_DESCS; i++, descs++)
|
||||
si_emit_shader_pointer(sctx, descs, base, false);
|
||||
}
|
||||
si_emit_shader_pointer(sctx, &sctx->vertex_buffers, sh_base[PIPE_SHADER_VERTEX], false);
|
||||
}
|
||||
|
|
@ -1591,15 +1650,10 @@ void si_emit_graphics_shader_userdata(struct si_context *sctx,
|
|||
void si_emit_compute_shader_userdata(struct si_context *sctx)
|
||||
{
|
||||
unsigned base = R_00B900_COMPUTE_USER_DATA_0;
|
||||
struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_FIRST_COMPUTE];
|
||||
|
||||
si_emit_shader_pointer(sctx, &sctx->const_buffers[PIPE_SHADER_COMPUTE].desc,
|
||||
base, false);
|
||||
si_emit_shader_pointer(sctx, &sctx->shader_buffers[PIPE_SHADER_COMPUTE].desc,
|
||||
base, false);
|
||||
si_emit_shader_pointer(sctx, &sctx->samplers[PIPE_SHADER_COMPUTE].views.desc,
|
||||
base, false);
|
||||
si_emit_shader_pointer(sctx, &sctx->images[PIPE_SHADER_COMPUTE].desc,
|
||||
base, false);
|
||||
for (unsigned i = 0; i < SI_NUM_SHADER_DESCS; ++i, ++descs)
|
||||
si_emit_shader_pointer(sctx, descs, base, false);
|
||||
}
|
||||
|
||||
/* INIT/DEINIT/UPLOAD */
|
||||
|
|
@ -1611,24 +1665,27 @@ void si_init_all_descriptors(struct si_context *sctx)
|
|||
|
||||
for (i = 0; i < SI_NUM_SHADERS; i++) {
|
||||
si_init_buffer_resources(&sctx->const_buffers[i],
|
||||
si_const_buffer_descriptors(sctx, i),
|
||||
SI_NUM_CONST_BUFFERS, SI_SGPR_CONST_BUFFERS,
|
||||
RADEON_USAGE_READ, RADEON_PRIO_CONST_BUFFER,
|
||||
&ce_offset);
|
||||
si_init_buffer_resources(&sctx->shader_buffers[i],
|
||||
si_shader_buffer_descriptors(sctx, i),
|
||||
SI_NUM_SHADER_BUFFERS, SI_SGPR_SHADER_BUFFERS,
|
||||
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RW_BUFFER,
|
||||
&ce_offset);
|
||||
|
||||
si_init_descriptors(&sctx->samplers[i].views.desc,
|
||||
si_init_descriptors(si_sampler_descriptors(sctx, i),
|
||||
SI_SGPR_SAMPLERS, 16, SI_NUM_SAMPLERS,
|
||||
null_texture_descriptor, &ce_offset);
|
||||
|
||||
si_init_descriptors(&sctx->images[i].desc,
|
||||
si_init_descriptors(si_image_descriptors(sctx, i),
|
||||
SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
|
||||
null_image_descriptor, &ce_offset);
|
||||
}
|
||||
|
||||
si_init_buffer_resources(&sctx->rw_buffers,
|
||||
&sctx->descriptors[SI_DESCS_RW_BUFFERS],
|
||||
SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
|
||||
RADEON_USAGE_READWRITE, RADEON_PRIO_RINGS_STREAMOUT,
|
||||
&ce_offset);
|
||||
|
|
@ -1662,20 +1719,13 @@ bool si_upload_graphics_shader_descriptors(struct si_context *sctx)
|
|||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SI_NUM_SHADERS; i++) {
|
||||
if (!si_upload_descriptors(sctx, &sctx->const_buffers[i].desc,
|
||||
&sctx->shader_userdata.atom) ||
|
||||
!si_upload_descriptors(sctx, &sctx->shader_buffers[i].desc,
|
||||
&sctx->shader_userdata.atom) ||
|
||||
!si_upload_descriptors(sctx, &sctx->samplers[i].views.desc,
|
||||
&sctx->shader_userdata.atom) ||
|
||||
!si_upload_descriptors(sctx, &sctx->images[i].desc,
|
||||
&sctx->shader_userdata.atom))
|
||||
for (i = 0; i < SI_DESCS_FIRST_COMPUTE; ++i) {
|
||||
if (!si_upload_descriptors(sctx, &sctx->descriptors[i],
|
||||
&sctx->shader_userdata.atom))
|
||||
return false;
|
||||
}
|
||||
return si_upload_descriptors(sctx, &sctx->rw_buffers.desc,
|
||||
&sctx->shader_userdata.atom) &&
|
||||
si_upload_vertex_buffer_descriptors(sctx);
|
||||
|
||||
return si_upload_vertex_buffer_descriptors(sctx);
|
||||
}
|
||||
|
||||
bool si_upload_compute_shader_descriptors(struct si_context *sctx)
|
||||
|
|
@ -1683,14 +1733,14 @@ bool si_upload_compute_shader_descriptors(struct si_context *sctx)
|
|||
/* Does not update rw_buffers as that is not needed for compute shaders
|
||||
* and the input buffer is using the same SGPR's anyway.
|
||||
*/
|
||||
return si_upload_descriptors(sctx,
|
||||
&sctx->const_buffers[PIPE_SHADER_COMPUTE].desc, NULL) &&
|
||||
si_upload_descriptors(sctx,
|
||||
&sctx->shader_buffers[PIPE_SHADER_COMPUTE].desc, NULL) &&
|
||||
si_upload_descriptors(sctx,
|
||||
&sctx->samplers[PIPE_SHADER_COMPUTE].views.desc, NULL) &&
|
||||
si_upload_descriptors(sctx,
|
||||
&sctx->images[PIPE_SHADER_COMPUTE].desc, NULL);
|
||||
unsigned i;
|
||||
|
||||
for (i = SI_DESCS_FIRST_COMPUTE; i < SI_NUM_DESCS; ++i) {
|
||||
if (!si_upload_descriptors(sctx, &sctx->descriptors[i], NULL))
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void si_release_all_descriptors(struct si_context *sctx)
|
||||
|
|
@ -1698,12 +1748,18 @@ void si_release_all_descriptors(struct si_context *sctx)
|
|||
int i;
|
||||
|
||||
for (i = 0; i < SI_NUM_SHADERS; i++) {
|
||||
si_release_buffer_resources(&sctx->const_buffers[i]);
|
||||
si_release_buffer_resources(&sctx->shader_buffers[i]);
|
||||
si_release_buffer_resources(&sctx->const_buffers[i],
|
||||
si_const_buffer_descriptors(sctx, i));
|
||||
si_release_buffer_resources(&sctx->shader_buffers[i],
|
||||
si_shader_buffer_descriptors(sctx, i));
|
||||
si_release_sampler_views(&sctx->samplers[i].views);
|
||||
si_release_image_views(&sctx->images[i]);
|
||||
}
|
||||
si_release_buffer_resources(&sctx->rw_buffers);
|
||||
si_release_buffer_resources(&sctx->rw_buffers,
|
||||
&sctx->descriptors[SI_DESCS_RW_BUFFERS]);
|
||||
|
||||
for (i = 0; i < SI_NUM_DESCS; ++i)
|
||||
si_release_descriptors(&sctx->descriptors[i]);
|
||||
si_release_descriptors(&sctx->vertex_buffers);
|
||||
}
|
||||
|
||||
|
|
@ -1719,5 +1775,9 @@ void si_all_descriptors_begin_new_cs(struct si_context *sctx)
|
|||
}
|
||||
si_buffer_resources_begin_new_cs(sctx, &sctx->rw_buffers);
|
||||
si_vertex_buffers_begin_new_cs(sctx);
|
||||
|
||||
for (i = 0; i < SI_NUM_DESCS; ++i)
|
||||
si_descriptors_begin_new_cs(sctx, &sctx->descriptors[i]);
|
||||
|
||||
si_shader_userdata_begin_new_cs(sctx);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -145,7 +145,6 @@ struct si_textures_info {
|
|||
};
|
||||
|
||||
struct si_images_info {
|
||||
struct si_descriptors desc;
|
||||
struct pipe_image_view views[SI_NUM_IMAGES];
|
||||
uint32_t compressed_colortex_mask;
|
||||
unsigned enabled_mask;
|
||||
|
|
@ -249,6 +248,7 @@ struct si_context {
|
|||
|
||||
/* shader descriptors */
|
||||
struct si_descriptors vertex_buffers;
|
||||
struct si_descriptors descriptors[SI_NUM_DESCS];
|
||||
struct si_buffer_resources rw_buffers;
|
||||
struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
|
||||
struct si_buffer_resources shader_buffers[SI_NUM_SHADERS];
|
||||
|
|
|
|||
|
|
@ -181,6 +181,31 @@ enum {
|
|||
SI_NUM_RW_BUFFERS,
|
||||
};
|
||||
|
||||
/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
|
||||
* are contiguous:
|
||||
*
|
||||
* 0 - rw buffers
|
||||
* 1 - vertex const buffers
|
||||
* 2 - vertex shader buffers
|
||||
* ...
|
||||
* 5 - fragment const buffers
|
||||
* ...
|
||||
* 21 - compute const buffers
|
||||
* ...
|
||||
*/
|
||||
#define SI_SHADER_DESCS_CONST_BUFFERS 0
|
||||
#define SI_SHADER_DESCS_SHADER_BUFFERS 1
|
||||
#define SI_SHADER_DESCS_SAMPLERS 2
|
||||
#define SI_SHADER_DESCS_IMAGES 3
|
||||
#define SI_NUM_SHADER_DESCS 4
|
||||
|
||||
#define SI_DESCS_RW_BUFFERS 0
|
||||
#define SI_DESCS_FIRST_SHADER 1
|
||||
#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
|
||||
PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
|
||||
#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
|
||||
SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
|
||||
|
||||
/* This represents descriptors in memory, such as buffer resources,
|
||||
* image resources, and sampler states.
|
||||
*/
|
||||
|
|
@ -214,7 +239,6 @@ struct si_descriptors {
|
|||
};
|
||||
|
||||
struct si_sampler_views {
|
||||
struct si_descriptors desc;
|
||||
struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
|
||||
void *sampler_states[SI_NUM_SAMPLERS];
|
||||
|
||||
|
|
@ -223,7 +247,6 @@ struct si_sampler_views {
|
|||
};
|
||||
|
||||
struct si_buffer_resources {
|
||||
struct si_descriptors desc;
|
||||
enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
|
||||
enum radeon_bo_priority priority;
|
||||
struct pipe_resource **buffers; /* this has num_buffers elements */
|
||||
|
|
|
|||
Loading…
Reference in New Issue