i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Fixes the following tests on CHV, BXT, and GLK: KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115
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@ -725,8 +725,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
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break;
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case nir_op_f2f64:
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case nir_op_f2i64:
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case nir_op_f2u64:
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case nir_op_i2f64:
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case nir_op_i2i64:
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case nir_op_u2f64:
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case nir_op_u2u64:
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/* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
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*
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* "When source or destination is 64b (...), regioning in Align1
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@ -754,12 +758,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
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case nir_op_f2f32:
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case nir_op_f2i32:
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case nir_op_f2u32:
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case nir_op_f2i64:
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case nir_op_f2u64:
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case nir_op_i2i32:
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case nir_op_i2i64:
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case nir_op_u2u32:
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case nir_op_u2u64:
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inst = bld.MOV(result, op[0]);
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inst->saturate = instr->dest.saturate;
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break;
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