i965/gen6 depth surface: calculate LOD being rendered to
(08ef1dd
for gen6)
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
parent
51b38106d7
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@ -783,6 +783,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
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uint32_t surftype;
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unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
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GLenum gl_target = params->depth.mt->target;
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unsigned int lod;
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switch (gl_target) {
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case GL_TEXTURE_CUBE_MAP_ARRAY:
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@ -806,6 +807,8 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
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NULL,
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&tile_mask_x, &tile_mask_y);
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lod = params->depth.level - params->depth.mt->first_level;
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/* 3DSTATE_DEPTH_BUFFER */
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{
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uint32_t tile_x = draw_x & tile_mask_x;
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@ -49,6 +49,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
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uint32_t surftype;
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unsigned int depth = 1;
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GLenum gl_target = GL_TEXTURE_2D;
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unsigned int lod;
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const struct intel_renderbuffer *irb = NULL;
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const struct gl_renderbuffer *rb = NULL;
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@ -97,6 +98,8 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
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break;
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}
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lod = irb ? irb->mt_level - irb->mt->first_level : 0;
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BEGIN_BATCH(7);
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OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
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OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
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