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nvc0: read MP counters of all GPCs on Fermi 

When a card has more than one GPC, the grid used by the compute
kernel which reads MP performance counters seems to be too small.
The consequence is that the kernel is not launched on all TPCs.

Increasing the grid size using the number of GPCs now launches
enough blocks and we can read MP performance counters of all TPCs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Samuel Pitoiset 2015-10-09 16:10:19 +02:00
parent 1825898e04
commit cef22f3490
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
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@ -528,7 +528,7 @@ nvc0_hw_sm_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
uint32_t mask;
uint32_t input[3];
const uint block[3] = { 32, is_nve4 ? 4 : 1, 1 };
const uint grid[3] = { screen->mp_count, 1, 1 };
const uint grid[3] = { screen->mp_count, screen->gpc_count, 1 };
unsigned c;
if (unlikely(!screen->pm.prog)) {