radv: precalculate tess ring sizes/offsets.
These are all static per device, so just calculate at device init time instead of preamble Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16392>
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@ -2811,6 +2811,10 @@ radv_device_init_hs_info(struct radv_device *device)
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}
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device->hs_offchip_param = hs_offchip_param;
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device->tess_factor_ring_size = 32768 * device->physical_device->rad_info.max_se;
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device->tess_offchip_ring_offset = align(device->tess_factor_ring_size, 64 * 1024);
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device->tess_offchip_ring_size = device->max_offchip_buffers * device->tess_offchip_block_dw_size * 4;
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}
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static VkResult
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@ -3664,8 +3668,7 @@ static void
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fill_geom_tess_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_positions,
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uint32_t esgs_ring_size, struct radeon_winsys_bo *esgs_ring_bo,
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uint32_t gsvs_ring_size, struct radeon_winsys_bo *gsvs_ring_bo,
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uint32_t tess_factor_ring_size, uint32_t tess_offchip_ring_offset,
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uint32_t tess_offchip_ring_size, struct radeon_winsys_bo *tess_rings_bo)
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struct radeon_winsys_bo *tess_rings_bo)
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{
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uint32_t *desc = &map[4];
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@ -3752,11 +3755,11 @@ fill_geom_tess_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_po
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if (tess_rings_bo) {
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uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
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uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
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uint64_t tess_offchip_va = tess_va + queue->device->tess_offchip_ring_offset;
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desc[0] = tess_va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
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desc[2] = tess_factor_ring_size;
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desc[2] = queue->device->tess_factor_ring_size;
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desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
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@ -3770,7 +3773,7 @@ fill_geom_tess_rings(struct radv_queue *queue, uint32_t *map, bool add_sample_po
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desc[4] = tess_offchip_va;
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desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
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desc[6] = tess_offchip_ring_size;
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desc[6] = queue->device->tess_offchip_ring_size;
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desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
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@ -3824,20 +3827,20 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
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static void
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radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
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unsigned tf_ring_size,
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struct radeon_winsys_bo *tess_rings_bo)
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{
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uint64_t tf_va;
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uint32_t tf_ring_size;
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if (!tess_rings_bo)
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return;
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tf_ring_size = queue->device->tess_factor_ring_size / 4;
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tf_va = radv_buffer_get_va(tess_rings_bo);
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radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
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if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
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radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size / 4));
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radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size));
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radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, tf_va >> 8);
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if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
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@ -3848,7 +3851,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
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}
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radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, queue->device->hs_offchip_param);
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} else {
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radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size / 4));
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radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size));
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radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE, tf_va >> 8);
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radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM, queue->device->hs_offchip_param);
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}
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@ -3979,8 +3982,6 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave,
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struct radeon_winsys_bo *gds_oa_bo = NULL;
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struct radeon_cmdbuf *dest_cs[3] = {0};
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bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
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unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
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unsigned tess_offchip_ring_offset;
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uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
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VkResult result = VK_SUCCESS;
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if (queue->qf == RADV_QUEUE_TRANSFER)
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@ -4002,9 +4003,6 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave,
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if (needs_sample_positions)
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add_sample_positions = true;
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}
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tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
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tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
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tess_offchip_ring_size = queue->device->max_offchip_buffers * queue->device->tess_offchip_block_dw_size * 4;
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scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
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if (scratch_size_per_wave)
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@ -4085,7 +4083,7 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave,
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if (add_tess_rings) {
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result = queue->device->ws->buffer_create(
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queue->device->ws, tess_offchip_ring_offset + tess_offchip_ring_size, 256,
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queue->device->ws, queue->device->tess_offchip_ring_offset + queue->device->tess_offchip_ring_size, 256,
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RADEON_DOMAIN_VRAM, ring_bo_flags, RADV_BO_PRIORITY_SCRATCH, 0, &tess_rings_bo);
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if (result != VK_SUCCESS)
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goto fail;
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@ -4154,8 +4152,7 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave,
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if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
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fill_geom_tess_rings(queue, map, add_sample_positions, esgs_ring_size, esgs_ring_bo,
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gsvs_ring_size, gsvs_ring_bo, tess_factor_ring_size,
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tess_offchip_ring_offset, tess_offchip_ring_size, tess_rings_bo);
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gsvs_ring_size, gsvs_ring_bo, tess_rings_bo);
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queue->device->ws->buffer_unmap(descriptor_bo);
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}
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@ -4198,7 +4195,7 @@ radv_get_preamble_cs(struct radv_queue *queue, uint32_t scratch_size_per_wave,
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radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size, gsvs_ring_bo,
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gsvs_ring_size);
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radv_emit_tess_factor_ring(queue, cs, tess_factor_ring_size, tess_rings_bo);
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radv_emit_tess_factor_ring(queue, cs, tess_rings_bo);
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radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
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radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave, compute_scratch_waves,
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compute_scratch_bo);
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@ -781,6 +781,9 @@ struct radv_device {
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uint32_t gs_table_depth;
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uint32_t hs_offchip_param;
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uint32_t max_offchip_buffers;
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uint32_t tess_offchip_ring_size;
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uint32_t tess_offchip_ring_offset;
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uint32_t tess_factor_ring_size;
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/* MSAA sample locations.
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* The first index is the sample index.
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