radeonsi: add an si_set_rw_shader_buffer convenience function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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556c4c42b7
commit
ce785f5ffd
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@ -1269,13 +1269,6 @@ static void si_set_constant_buffer(struct si_context *sctx,
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sctx->descriptors_dirty |= 1u << descriptors_idx;
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}
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void si_set_rw_buffer(struct si_context *sctx,
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uint slot, const struct pipe_constant_buffer *input)
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{
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si_set_constant_buffer(sctx, &sctx->rw_buffers,
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SI_DESCS_RW_BUFFERS, slot, input);
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}
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static void si_pipe_set_constant_buffer(struct pipe_context *ctx,
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enum pipe_shader_type shader, uint slot,
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const struct pipe_constant_buffer *input)
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@ -1310,6 +1303,49 @@ void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
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/* SHADER BUFFERS */
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static void si_set_shader_buffer(struct si_context *sctx,
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struct si_buffer_resources *buffers,
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unsigned descriptors_idx,
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uint slot, const struct pipe_shader_buffer *sbuffer,
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enum radeon_bo_priority priority)
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{
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struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
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uint32_t *desc = descs->list + slot * 4;
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if (!sbuffer || !sbuffer->buffer) {
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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memset(desc, 0, sizeof(uint32_t) * 4);
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buffers->enabled_mask &= ~(1u << slot);
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sctx->descriptors_dirty |= 1u << descriptors_idx;
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return;
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}
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struct r600_resource *buf = r600_resource(sbuffer->buffer);
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uint64_t va = buf->gpu_address + sbuffer->buffer_offset;
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(0);
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desc[2] = sbuffer->buffer_size;
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desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
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S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
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S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
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S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
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radeon_add_to_gfx_buffer_list_check_mem(sctx, buf,
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buffers->shader_usage,
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priority, true);
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buffers->enabled_mask |= 1u << slot;
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sctx->descriptors_dirty |= 1u << descriptors_idx;
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util_range_add(&buf->valid_buffer_range, sbuffer->buffer_offset,
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sbuffer->buffer_offset + sbuffer->buffer_size);
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}
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static void si_set_shader_buffers(struct pipe_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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@ -1317,53 +1353,20 @@ static void si_set_shader_buffers(struct pipe_context *ctx,
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
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struct si_descriptors *descs = si_const_and_shader_buffer_descriptors(sctx, shader);
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unsigned descriptors_idx = si_const_and_shader_buffer_descriptors_idx(shader);
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unsigned i;
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assert(start_slot + count <= SI_NUM_SHADER_BUFFERS);
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for (i = 0; i < count; ++i) {
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const struct pipe_shader_buffer *sbuffer = sbuffers ? &sbuffers[i] : NULL;
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struct r600_resource *buf;
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unsigned slot = si_get_shaderbuf_slot(start_slot + i);
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uint32_t *desc = descs->list + slot * 4;
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uint64_t va;
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if (!sbuffer || !sbuffer->buffer) {
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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memset(desc, 0, sizeof(uint32_t) * 4);
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buffers->enabled_mask &= ~(1u << slot);
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sctx->descriptors_dirty |=
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1u << si_const_and_shader_buffer_descriptors_idx(shader);
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continue;
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}
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if (sbuffer && sbuffer->buffer)
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r600_resource(sbuffer->buffer)->bind_history |= PIPE_BIND_SHADER_BUFFER;
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buf = r600_resource(sbuffer->buffer);
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va = buf->gpu_address + sbuffer->buffer_offset;
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desc[0] = va;
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desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
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S_008F04_STRIDE(0);
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desc[2] = sbuffer->buffer_size;
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desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
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S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
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S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
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S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
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radeon_add_to_gfx_buffer_list_check_mem(sctx, buf,
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buffers->shader_usage,
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buffers->priority, true);
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buf->bind_history |= PIPE_BIND_SHADER_BUFFER;
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buffers->enabled_mask |= 1u << slot;
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sctx->descriptors_dirty |=
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1u << si_const_and_shader_buffer_descriptors_idx(shader);
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util_range_add(&buf->valid_buffer_range, sbuffer->buffer_offset,
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sbuffer->buffer_offset + sbuffer->buffer_size);
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si_set_shader_buffer(sctx, buffers, descriptors_idx, slot, sbuffer,
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buffers->priority);
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}
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}
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@ -1386,6 +1389,20 @@ void si_get_shader_buffers(struct si_context *sctx,
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/* RING BUFFERS */
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void si_set_rw_buffer(struct si_context *sctx,
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uint slot, const struct pipe_constant_buffer *input)
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{
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si_set_constant_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS,
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slot, input);
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}
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void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
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const struct pipe_shader_buffer *sbuffer)
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{
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si_set_shader_buffer(sctx, &sctx->rw_buffers, SI_DESCS_RW_BUFFERS,
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slot, sbuffer, RADEON_PRIO_SHADER_RW_BUFFER);
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}
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void si_set_ring_buffer(struct si_context *sctx, uint slot,
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struct pipe_resource *buffer,
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unsigned stride, unsigned num_records,
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@ -474,6 +474,8 @@ void si_emit_graphics_shader_pointers(struct si_context *sctx);
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void si_emit_compute_shader_pointers(struct si_context *sctx);
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void si_set_rw_buffer(struct si_context *sctx,
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uint slot, const struct pipe_constant_buffer *input);
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void si_set_rw_shader_buffer(struct si_context *sctx, uint slot,
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const struct pipe_shader_buffer *sbuffer);
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void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx,
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uint64_t new_active_mask);
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void si_set_active_descriptors_for_shader(struct si_context *sctx,
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