i965: Fix render target writes on Ivybridge.
Ivybridge shifts the data port messages by one bit. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
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@ -509,7 +509,19 @@ static void brw_set_dp_write_message( struct brw_compile *p,
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struct intel_context *intel = &brw->intel;
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brw_set_src1(p, insn, brw_imm_ud(0));
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if (intel->gen >= 6) {
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if (intel->gen >= 7) {
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insn->bits3.gen7_dp.binding_table_index = binding_table_index;
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insn->bits3.gen7_dp.msg_control = msg_control;
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insn->bits3.gen7_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
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insn->bits3.gen7_dp.msg_type = msg_type;
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insn->bits3.gen7_dp.header_present = header_present;
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insn->bits3.gen7_dp.response_length = response_length;
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insn->bits3.gen7_dp.msg_length = msg_length;
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insn->bits3.gen7_dp.end_of_thread = end_of_thread;
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/* We always use the render cache for write messages */
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insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
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} else if (intel->gen == 6) {
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insn->bits3.gen6_dp.binding_table_index = binding_table_index;
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insn->bits3.gen6_dp.msg_control = msg_control;
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insn->bits3.gen6_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
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@ -1728,6 +1728,22 @@ struct brw_instruction
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GLuint end_of_thread:1;
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} gen6_dp;
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/* See volume vol5c.2 sections 2.11.2.1.5 and 2.11.21.2.2. */
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struct {
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GLuint binding_table_index:8;
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GLuint msg_control:3;
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GLuint slot_group_select:1;
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GLuint pixel_scoreboard_clear:1;
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GLuint pad0:1;
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GLuint msg_type:4;
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GLuint pad1:1;
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GLuint header_present:1;
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GLuint response_length:5;
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GLuint msg_length:4;
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GLuint pad2:2;
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GLuint end_of_thread:1;
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} gen7_dp;
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struct {
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GLuint function_control:16;
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GLuint response_length:4;
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