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r600g/llvm:translate ARL opcode to a simple cast 

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Vincent Lejeune 2013-01-08 22:46:37 +01:00 committed by Tom Stellard
parent 7d532800d8
commit ce34ff1ad7
1 changed files with 12 additions and 2 deletions
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14
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
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@ -800,6 +800,17 @@ static void emit_not(
emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
}
static void emit_arl(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
floor_index, bld_base->base.int_elem_type , "");
}
static void emit_and(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
@ -1119,8 +1130,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_readonly;
bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;
bld_base->op_actions[TGSI_OPCODE_BRK].emit = brk_emit;