i965/gen6: Fix scissors using invalid STATE_BASE_ADDRESS.
The scissor state was incorrectly in a .prepare function instead of .emit, so the packet would end up in the batch before the STATE_BASE_ADDRESS. It appears that this doesn't actually hurt, as the scissor address gets dereferenced according to the current SBA at draw time.
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@ -31,7 +31,7 @@
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#include "intel_batchbuffer.h"
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static void
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gen6_prepare_scissor_state(struct brw_context *brw)
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gen6_upload_scissor_state(struct brw_context *brw)
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{
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struct intel_context *intel = &brw->intel;
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struct gl_context *ctx = &intel->ctx;
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@ -89,5 +89,5 @@ const struct brw_tracked_state gen6_scissor_state = {
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.brw = BRW_NEW_BATCH,
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.cache = 0,
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},
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.prepare = gen6_prepare_scissor_state,
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.emit = gen6_upload_scissor_state,
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};
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