intel/isl: Implement D16_UNORM workarounds.
GEN:BUG:14010455700 (lineage 1808121037): "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501. GEN:BUG:1806527549: "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM." This one could fix a GPU hang in some workloads. v2: Implement WA in isl and add another similar WA (Jason). v3: Add flushes before changing chicken registers (Jason) v4: Depth flush and stall + end of pipe sync when changing registers (Jason). Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
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@ -1056,7 +1056,8 @@ struct iris_depth_buffer_state {
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uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
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uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
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GENX(3DSTATE_STENCIL_BUFFER_length) +
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GENX(3DSTATE_STENCIL_BUFFER_length) +
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GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
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GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
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GENX(3DSTATE_CLEAR_PARAMS_length)];
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GENX(3DSTATE_CLEAR_PARAMS_length) +
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GENX(MI_LOAD_REGISTER_IMM_length) * 2];
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};
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};
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/**
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/**
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@ -5900,7 +5901,22 @@ iris_upload_dirty_render_state(struct iris_context *ice,
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* first.
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* first.
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*/
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*/
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uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4;
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uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4;
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uint32_t cso_z_size = sizeof(cso_z->packets) - clear_length;
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uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;;
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#if GEN_GEN == 12
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/* GEN:BUG:14010455700
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*
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* ISL will change some CHICKEN registers depending on the depth surface
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* format, along with emitting the depth and stencil packets. In that
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* case, we want to do a depth flush and stall, so the pipeline is not
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* using these settings while we change the registers.
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*/
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iris_emit_end_of_pipe_sync(batch,
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"Workaround: Stop pipeline for 14010455700",
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PIPE_CONTROL_DEPTH_STALL |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH);
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#endif
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iris_batch_emit(batch, cso_z->packets, cso_z_size);
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iris_batch_emit(batch, cso_z->packets, cso_z_size);
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if (GEN_GEN >= 12) {
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if (GEN_GEN >= 12) {
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/* GEN:BUG:1408224581
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/* GEN:BUG:1408224581
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@ -7032,6 +7032,16 @@
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<field name="CL Primitives Count Report" start="0" end="63" type="uint"/>
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<field name="CL Primitives Count Report" start="0" end="63" type="uint"/>
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</register>
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</register>
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<register name="COMMON_SLICE_CHICKEN1" length="1" num="0x7010">
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<field name="HIZ Plane Optimization disable bit" start="9" end="9" type="bool"/>
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<field name="HIZ Plane Optimization disable bit Mask" start="25" end="25" type="bool"/>
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</register>
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<register name="HIZ_CHICKEN" length="1" num="0x7018">
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<field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/>
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<field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/>
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</register>
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<register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
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<register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
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<field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/>
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<field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/>
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<field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/>
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<field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/>
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@ -223,6 +223,10 @@ isl_device_init(struct isl_device *dev,
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dev->ds.hiz_offset = 0;
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dev->ds.hiz_offset = 0;
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}
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}
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if (ISL_DEV_GEN(dev) >= 12) {
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dev->ds.size += GEN12_MI_LOAD_REGISTER_IMM_length * 4 * 2;
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}
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isl_device_setup_mocs(dev);
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isl_device_setup_mocs(dev);
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}
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}
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@ -255,6 +255,50 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
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GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
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GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz);
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dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
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dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length);
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#if GEN_GEN == 12
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/* GEN:BUG:14010455700
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*
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* To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface
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* Format is D16_UNORM , surface type is not NULL & 1X_MSAA”.
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*/
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bool enable_14010455700 =
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info->depth_surf && info->depth_surf->samples == 1 &&
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db.SurfaceType != SURFTYPE_NULL && db.SurfaceFormat == D16_UNORM;
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struct GENX(COMMON_SLICE_CHICKEN1) chicken1 = {
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.HIZPlaneOptimizationdisablebit = enable_14010455700,
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.HIZPlaneOptimizationdisablebitMask = true,
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};
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uint32_t chicken1_dw;
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GENX(COMMON_SLICE_CHICKEN1_pack)(NULL, &chicken1_dw, &chicken1);
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struct GENX(MI_LOAD_REGISTER_IMM) lri = {
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GENX(MI_LOAD_REGISTER_IMM_header),
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.RegisterOffset = GENX(COMMON_SLICE_CHICKEN1_num),
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.DataDWord = chicken1_dw,
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};
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GENX(MI_LOAD_REGISTER_IMM_pack)(NULL, dw, &lri);
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dw += GENX(MI_LOAD_REGISTER_IMM_length);
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/* GEN:BUG:1806527549
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*
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* Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM.
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*/
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struct GENX(HIZ_CHICKEN) hiz_chicken = {
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.HZDepthTestLEGEOptimizationDisable = db.SurfaceFormat == D16_UNORM,
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.HZDepthTestLEGEOptimizationDisableMask = true,
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};
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uint32_t hiz_chicken_dw;
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GENX(HIZ_CHICKEN_pack)(NULL, &hiz_chicken_dw, &hiz_chicken);
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struct GENX(MI_LOAD_REGISTER_IMM) lri2 = {
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GENX(MI_LOAD_REGISTER_IMM_header),
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.RegisterOffset = GENX(HIZ_CHICKEN_num),
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.DataDWord = hiz_chicken_dw,
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};
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GENX(MI_LOAD_REGISTER_IMM_pack)(NULL, dw, &lri2);
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dw += GENX(MI_LOAD_REGISTER_IMM_length);
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#endif
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GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
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GENX(3DSTATE_CLEAR_PARAMS_pack)(NULL, dw, &clear);
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dw += GENX(3DSTATE_CLEAR_PARAMS_length);
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dw += GENX(3DSTATE_CLEAR_PARAMS_length);
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#endif
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#endif
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@ -5160,8 +5160,6 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
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att_state->pending_load_aspects = 0;
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att_state->pending_load_aspects = 0;
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}
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}
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cmd_buffer_emit_depth_stencil(cmd_buffer);
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#if GEN_GEN >= 11
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#if GEN_GEN >= 11
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/* The PIPE_CONTROL command description says:
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/* The PIPE_CONTROL command description says:
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*
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*
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@ -5175,6 +5173,23 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer,
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ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
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ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
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ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
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#endif
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#endif
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#if GEN_GEN == 12
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/* GEN:BUG:14010455700
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*
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* ISL will change some CHICKEN registers depending on the depth surface
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* format, along with emitting the depth and stencil packets. In that case,
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* we want to do a depth flush and stall, so the pipeline is not using these
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* settings while we change the registers.
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*/
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cmd_buffer->state.pending_pipe_bits |=
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_DEPTH_STALL_BIT |
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ANV_PIPE_END_OF_PIPE_SYNC_BIT;
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genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
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#endif
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cmd_buffer_emit_depth_stencil(cmd_buffer);
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}
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}
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static enum blorp_filter
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static enum blorp_filter
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