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winsys/radeon: fix indentation 

Can we please keep it clean and avoid ending up in messy situation
like ddx.

Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
This commit is contained in:
Jerome Glisse 2014-07-24 17:30:31 -04:00
parent 989d2e3709
commit cce58147eb
1 changed files with 29 additions and 29 deletions
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58
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
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@ -155,7 +155,7 @@ static struct radeon_winsys_cs *
radeon_drm_cs_create(struct radeon_winsys *rws,
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
struct pipe_fence_handle **fence),
void *flush_ctx,
struct radeon_winsys_cs_handle *trace_buf)
{
@ -196,10 +196,10 @@ radeon_drm_cs_create(struct radeon_winsys *rws,
#define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
static INLINE void update_reloc(struct drm_radeon_cs_reloc *reloc,
enum radeon_bo_domain rd,
enum radeon_bo_domain wd,
unsigned priority,
enum radeon_bo_domain *added_domains)
enum radeon_bo_domain rd,
enum radeon_bo_domain wd,
unsigned priority,
enum radeon_bo_domain *added_domains)
{
*added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
@ -434,33 +434,33 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
switch (cs->base.ring_type) {
case RING_DMA:
/* pad DMA ring to 8 DWs */
if (cs->ws->info.chip_class <= SI) {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
} else {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0x00000000); /* NOP packet */
}
break;
/* pad DMA ring to 8 DWs */
if (cs->ws->info.chip_class <= SI) {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0xf0000000); /* NOP packet */
} else {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0x00000000); /* NOP packet */
}
break;
case RING_GFX:
/* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
* r6xx, requires at least 4 dw alignment to avoid a hw bug.
*/
if (cs->ws->info.chip_class <= SI) {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
} else {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
}
break;
/* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
* r6xx, requires at least 4 dw alignment to avoid a hw bug.
*/
if (cs->ws->info.chip_class <= SI) {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
} else {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */
}
break;
case RING_UVD:
while (rcs->cdw & 15)
OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
break;
while (rcs->cdw & 15)
OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */
break;
default:
break;
break;
}
if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {