intel/fs: Fix MOV_INDIRECT and BROADCAST of Q types on Gen11+
The immediate case is pretty uncommon to see but it can happen, in
theory. BROADCAST is typically used to uniformize values and those are
usually 32-bit. However, it does come up in some subgroup ops.
Fixes: 49c21802cb
"intel/compiler: Split has_64bit_types into float/int"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6211>
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@ -3361,9 +3361,18 @@ brw_broadcast(struct brw_codegen *p,
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* asserting would be mean.
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* asserting would be mean.
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*/
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*/
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const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
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const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
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brw_MOV(p, dst,
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src = align1 ? stride(suboffset(src, i), 0, 1, 0) :
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(align1 ? stride(suboffset(src, i), 0, 1, 0) :
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stride(suboffset(src, 4 * i), 0, 4, 1);
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stride(suboffset(src, 4 * i), 0, 4, 1)));
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if (type_sz(src.type) > 4 && !devinfo->has_64bit_float) {
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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subscript(src, BRW_REGISTER_TYPE_D, 0));
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brw_set_default_swsb(p, tgl_swsb_null());
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
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subscript(src, BRW_REGISTER_TYPE_D, 1));
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} else {
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brw_MOV(p, dst, src);
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}
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} else {
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} else {
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/* From the Haswell PRM section "Register Region Restrictions":
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/* From the Haswell PRM section "Register Region Restrictions":
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*
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*
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@ -3412,7 +3421,8 @@ brw_broadcast(struct brw_codegen *p,
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/* Use indirect addressing to fetch the specified component. */
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/* Use indirect addressing to fetch the specified component. */
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if (type_sz(src.type) > 4 &&
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if (type_sz(src.type) > 4 &&
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(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
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(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
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!devinfo->has_64bit_float)) {
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/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
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/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
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*
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*
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* "When source or destination datatype is 64b or operation is
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* "When source or destination datatype is 64b or operation is
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@ -468,7 +468,15 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
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reg.nr = imm_byte_offset / REG_SIZE;
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reg.nr = imm_byte_offset / REG_SIZE;
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reg.subnr = imm_byte_offset % REG_SIZE;
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reg.subnr = imm_byte_offset % REG_SIZE;
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brw_MOV(p, dst, reg);
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if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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subscript(reg, BRW_REGISTER_TYPE_D, 0));
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brw_set_default_swsb(p, tgl_swsb_null());
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
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subscript(reg, BRW_REGISTER_TYPE_D, 1));
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} else {
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brw_MOV(p, dst, reg);
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}
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} else {
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} else {
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/* Prior to Broadwell, there are only 8 address registers. */
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/* Prior to Broadwell, there are only 8 address registers. */
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assert(inst->exec_size <= 8 || devinfo->gen >= 8);
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assert(inst->exec_size <= 8 || devinfo->gen >= 8);
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