intel/fs: Support min_lod parameters on texture instructions
We have to lower some shadow instructions because they don't exist in hardware and we have to lower txb+offset+clamp because the message gets too big and we run into the sampler message length limit of 11 regs. Acked-by: Ian Romanick <ian.d.romanick@intel.com>
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@ -811,6 +811,8 @@ enum tex_logical_srcs {
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TEX_LOGICAL_SRC_LOD,
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/** dPdy if the operation takes explicit derivatives */
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TEX_LOGICAL_SRC_LOD2,
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/** Min LOD */
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TEX_LOGICAL_SRC_MIN_LOD,
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/** Sample index */
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TEX_LOGICAL_SRC_SAMPLE_INDEX,
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/** MCS data */
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@ -4472,6 +4472,7 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
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const fs_reg &coordinate,
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const fs_reg &shadow_c,
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fs_reg lod, const fs_reg &lod2,
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const fs_reg &min_lod,
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const fs_reg &sample_index,
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const fs_reg &mcs,
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const fs_reg &surface,
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@ -4682,6 +4683,15 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
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bld.MOV(sources[length++], offset(coordinate, bld, i));
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}
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if (min_lod.file != BAD_FILE) {
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/* Account for all of the missing coordinate sources */
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length += 4 - coord_components;
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if (op == SHADER_OPCODE_TXD)
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length += (3 - grad_components) * 2;
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bld.MOV(sources[length++], min_lod);
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}
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int mlen;
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if (reg_width == 2)
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mlen = length * reg_width - header_size;
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@ -4713,6 +4723,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
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const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C];
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const fs_reg &lod = inst->src[TEX_LOGICAL_SRC_LOD];
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const fs_reg &lod2 = inst->src[TEX_LOGICAL_SRC_LOD2];
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const fs_reg &min_lod = inst->src[TEX_LOGICAL_SRC_MIN_LOD];
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const fs_reg &sample_index = inst->src[TEX_LOGICAL_SRC_SAMPLE_INDEX];
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const fs_reg &mcs = inst->src[TEX_LOGICAL_SRC_MCS];
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const fs_reg &surface = inst->src[TEX_LOGICAL_SRC_SURFACE];
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@ -4725,7 +4736,8 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
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if (devinfo->gen >= 7) {
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lower_sampler_logical_send_gen7(bld, inst, op, coordinate,
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shadow_c, lod, lod2, sample_index,
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shadow_c, lod, lod2, min_lod,
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sample_index,
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mcs, surface, sampler, tg4_offset,
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coord_components, grad_components);
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} else if (devinfo->gen >= 5) {
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@ -5262,6 +5274,14 @@ static unsigned
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get_sampler_lowered_simd_width(const struct gen_device_info *devinfo,
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const fs_inst *inst)
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{
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/* If we have a min_lod parameter on anything other than a simple sample
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* message, it will push it over 5 arguments and we have to fall back to
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* SIMD8.
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*/
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if (inst->opcode != SHADER_OPCODE_TEX &&
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inst->components_read(TEX_LOGICAL_SRC_MIN_LOD))
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return 8;
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/* Calculate the number of coordinate components that have to be present
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* assuming that additional arguments follow the texel coordinates in the
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* message payload. On IVB+ there is no need for padding, on ILK-SNB we
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@ -2968,7 +2968,7 @@ fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
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/* Emit the instruction. */
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const fs_reg srcs[] = { coords, fs_reg(), brw_imm_ud(0), fs_reg(),
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sample, mcs,
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fs_reg(), sample, mcs,
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brw_imm_ud(surface), brw_imm_ud(0),
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fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
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STATIC_ASSERT(ARRAY_SIZE(srcs) == TEX_LOGICAL_NUM_SRCS);
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@ -4792,6 +4792,10 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
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break;
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}
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break;
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case nir_tex_src_min_lod:
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srcs[TEX_LOGICAL_SRC_MIN_LOD] =
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retype(get_nir_src_imm(instr->src[i].src), BRW_REGISTER_TYPE_F);
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break;
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case nir_tex_src_ms_index:
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srcs[TEX_LOGICAL_SRC_SAMPLE_INDEX] = retype(src, BRW_REGISTER_TYPE_UD);
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break;
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@ -656,6 +656,9 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir)
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.lower_txf_offset = true,
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.lower_rect_offset = true,
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.lower_txd_cube_map = true,
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.lower_txb_shadow_clamp = true,
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.lower_txd_shadow_clamp = true,
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.lower_txd_offset_clamp = true,
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};
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OPT(nir_lower_tex, &tex_options);
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