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gm107/ir: fix sign bit emission for FADD32I 

When emitting OP_SUB, the sign bit for FADD and FADD32I is not
at the same position. It's at position 45 for FADD but 51 for FADD32I.

This fixes the following piglit test:
tests/spec/arb_fragment_program/fdo30337b.shader_test

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Samuel Pitoiset 2016-07-04 13:12:20 +02:00
parent ac772b24a1
commit cb828b7b18
1 changed files with 6 additions and 3 deletions
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9
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
View File

@ -1234,6 +1234,9 @@ CodeEmitterGM107::emitFADD()
emitABS(0x2e, insn->src(0));
emitNEG(0x2d, insn->src(1));
emitFMZ(0x2c, 1);
if (insn->op == OP_SUB)
code[1] ^= 0x00002000;
} else {
emitInsn(0x08000000);
emitABS(0x39, insn->src(1));
@ -1243,10 +1246,10 @@ CodeEmitterGM107::emitFADD()
emitNEG(0x35, insn->src(1));
emitCC (0x34);
emitIMMD(0x14, 32, insn->src(1));
}
if (insn->op == OP_SUB)
code[1] ^= 0x00002000;
if (insn->op == OP_SUB)
code[1] ^= 0x00080000;
}
emitGPR(0x08, insn->src(0));
emitGPR(0x00, insn->def(0));