freedreno/a3xx: 3d/array textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
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eea1cdf687
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ca29c4c3b0
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@ -175,7 +175,24 @@ fd3_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
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/* when emitted, A3XX_TEX_CONST_2_INDX() must be OR'd in: */
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/* when emitted, A3XX_TEX_CONST_2_INDX() must be OR'd in: */
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so->texconst2 =
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so->texconst2 =
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A3XX_TEX_CONST_2_PITCH(rsc->slices[lvl].pitch * rsc->cpp);
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A3XX_TEX_CONST_2_PITCH(rsc->slices[lvl].pitch * rsc->cpp);
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so->texconst3 = 0x00000000; /* ??? */
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switch (prsc->target) {
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case PIPE_TEXTURE_1D_ARRAY:
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case PIPE_TEXTURE_2D_ARRAY:
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so->texconst3 =
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A3XX_TEX_CONST_3_DEPTH(u_minify(prsc->array_size, lvl)) |
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A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[0].size0) |
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A3XX_TEX_CONST_3_LAYERSZ2(rsc->slices[0].size0);
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break;
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case PIPE_TEXTURE_3D:
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so->texconst3 =
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A3XX_TEX_CONST_3_DEPTH(u_minify(prsc->depth0, lvl)) |
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A3XX_TEX_CONST_3_LAYERSZ1(rsc->slices[0].size0) |
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A3XX_TEX_CONST_3_LAYERSZ2(rsc->slices[0].size0);
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break;
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default:
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so->texconst3 = 0x00000000;
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break;
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}
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return &so->base;
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return &so->base;
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}
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}
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@ -226,7 +226,7 @@ struct fd_context {
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* tiling commands, we need to make sure we need to leave enough
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* tiling commands, we need to make sure we need to leave enough
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* room at the end to append the tiling commands when we flush.
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* room at the end to append the tiling commands when we flush.
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* 0x7000 dwords should be a couple times more than we ever need
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* 0x7000 dwords should be a couple times more than we ever need
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* so should be a nice concervative threshold.
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* so should be a nice conservative threshold.
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*/
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*/
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#define FD_TILING_COMMANDS_DWORDS 0x7000
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#define FD_TILING_COMMANDS_DWORDS 0x7000
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@ -215,6 +215,36 @@ setup_slices(struct fd_resource *rsc)
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return size;
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return size;
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}
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}
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/* 2d array and 3d textures seem to want their layers aligned to
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* page boundaries
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*/
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static uint32_t
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setup_slices_array(struct fd_resource *rsc)
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{
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struct pipe_resource *prsc = &rsc->base.b;
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uint32_t level, size = 0;
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uint32_t width = prsc->width0;
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uint32_t height = prsc->height0;
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uint32_t depth = prsc->depth0;
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for (level = 0; level <= prsc->last_level; level++) {
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struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
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uint32_t aligned_width = align(width, 32);
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slice->pitch = aligned_width;
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slice->offset = size;
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slice->size0 = align(slice->pitch * height * rsc->cpp, 4096);
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size += slice->size0 * depth * prsc->array_size;
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width = u_minify(width, 1);
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height = u_minify(height, 1);
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depth = u_minify(depth, 1);
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}
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return size;
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}
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/**
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/**
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* Create a new texture object, using the given template info.
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* Create a new texture object, using the given template info.
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*/
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*/
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@ -246,7 +276,16 @@ fd_resource_create(struct pipe_screen *pscreen,
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assert(rsc->cpp);
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assert(rsc->cpp);
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size = setup_slices(rsc);
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switch (tmpl->target) {
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case PIPE_TEXTURE_3D:
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case PIPE_TEXTURE_1D_ARRAY:
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case PIPE_TEXTURE_2D_ARRAY:
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size = setup_slices_array(rsc);
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break;
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default:
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size = setup_slices(rsc);
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break;
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}
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realloc_bo(rsc, size);
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realloc_bo(rsc, size);
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if (!rsc->bo)
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if (!rsc->bo)
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@ -1094,6 +1094,11 @@ get_tex_info(struct ir3_compile_context *ctx,
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.flags = IR3_INSTR_S,
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.flags = IR3_INSTR_S,
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};
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};
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static const struct tex_info tex1da = {
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.order = { 0, -1, 2, -1 }, /* coord.xz */
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.flags = IR3_INSTR_A,
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};
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static const struct tex_info tex2d = {
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static const struct tex_info tex2d = {
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.order = { 0, 1, -1, -1 }, /* coord.xy */
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.order = { 0, 1, -1, -1 }, /* coord.xy */
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.src_wrmask = TGSI_WRITEMASK_XY,
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.src_wrmask = TGSI_WRITEMASK_XY,
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@ -1104,6 +1109,11 @@ get_tex_info(struct ir3_compile_context *ctx,
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.flags = IR3_INSTR_S,
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.flags = IR3_INSTR_S,
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};
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};
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static const struct tex_info tex2da = {
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.order = { 0, 1, 2, -1 }, /* coord.xyz */
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.flags = IR3_INSTR_A,
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};
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static const struct tex_info tex3d = {
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static const struct tex_info tex3d = {
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.order = { 0, 1, 2, -1 }, /* coord.xyz */
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.order = { 0, 1, 2, -1 }, /* coord.xyz */
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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@ -1124,6 +1134,11 @@ get_tex_info(struct ir3_compile_context *ctx,
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.flags = IR3_INSTR_P | IR3_INSTR_S,
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.flags = IR3_INSTR_P | IR3_INSTR_S,
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};
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};
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static const struct tex_info txp1da = {
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.order = { 0, -1, 2, 3 }, /* coord.xzw */
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.flags = IR3_INSTR_P | IR3_INSTR_A,
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};
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static const struct tex_info txp2d = {
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static const struct tex_info txp2d = {
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.order = { 0, 1, 3, -1 }, /* coord.xyw */
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.order = { 0, 1, 3, -1 }, /* coord.xyw */
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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.src_wrmask = TGSI_WRITEMASK_XYZ,
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@ -1134,6 +1149,11 @@ get_tex_info(struct ir3_compile_context *ctx,
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.flags = IR3_INSTR_P | IR3_INSTR_S,
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.flags = IR3_INSTR_P | IR3_INSTR_S,
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};
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};
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static const struct tex_info txp2da = {
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.order = { 0, 1, 2, 3 }, /* coord.xyzw */
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.flags = IR3_INSTR_P | IR3_INSTR_A,
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};
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static const struct tex_info txp3d = {
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static const struct tex_info txp3d = {
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.order = { 0, 1, 2, 3 }, /* coord.xyzw */
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.order = { 0, 1, 2, 3 }, /* coord.xyzw */
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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.src_wrmask = TGSI_WRITEMASK_XYZW,
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@ -1151,12 +1171,16 @@ get_tex_info(struct ir3_compile_context *ctx,
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return &tex1d;
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return &tex1d;
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case TGSI_TEXTURE_SHADOW1D:
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case TGSI_TEXTURE_SHADOW1D:
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return &tex1ds;
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return &tex1ds;
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case TGSI_TEXTURE_1D_ARRAY:
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return &tex1da;
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case TGSI_TEXTURE_2D:
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case TGSI_TEXTURE_2D:
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case TGSI_TEXTURE_RECT:
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case TGSI_TEXTURE_RECT:
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return &tex2d;
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return &tex2d;
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case TGSI_TEXTURE_SHADOW2D:
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case TGSI_TEXTURE_SHADOW2D:
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case TGSI_TEXTURE_SHADOWRECT:
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case TGSI_TEXTURE_SHADOWRECT:
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return &tex2ds;
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return &tex2ds;
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case TGSI_TEXTURE_2D_ARRAY:
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return &tex2da;
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case TGSI_TEXTURE_3D:
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case TGSI_TEXTURE_3D:
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case TGSI_TEXTURE_CUBE:
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case TGSI_TEXTURE_CUBE:
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return &tex3d;
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return &tex3d;
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@ -1174,12 +1198,16 @@ get_tex_info(struct ir3_compile_context *ctx,
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return &txp1d;
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return &txp1d;
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case TGSI_TEXTURE_SHADOW1D:
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case TGSI_TEXTURE_SHADOW1D:
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return &txp1ds;
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return &txp1ds;
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case TGSI_TEXTURE_1D_ARRAY:
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return &txp1da;
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case TGSI_TEXTURE_2D:
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case TGSI_TEXTURE_2D:
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case TGSI_TEXTURE_RECT:
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case TGSI_TEXTURE_RECT:
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return &txp2d;
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return &txp2d;
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case TGSI_TEXTURE_SHADOW2D:
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case TGSI_TEXTURE_SHADOW2D:
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case TGSI_TEXTURE_SHADOWRECT:
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case TGSI_TEXTURE_SHADOWRECT:
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return &txp2ds;
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return &txp2ds;
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case TGSI_TEXTURE_2D_ARRAY:
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return &txp2da;
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case TGSI_TEXTURE_3D:
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case TGSI_TEXTURE_3D:
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case TGSI_TEXTURE_CUBE:
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case TGSI_TEXTURE_CUBE:
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return &txp3d;
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return &txp3d;
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@ -1203,6 +1231,18 @@ static bool check_swiz(struct tgsi_src_register *src, const int8_t order[4])
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return true;
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return true;
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}
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}
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static bool is_1d(unsigned tex)
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{
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switch (tex) {
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case TGSI_TEXTURE_1D:
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case TGSI_TEXTURE_SHADOW1D:
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case TGSI_TEXTURE_1D_ARRAY:
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return true;
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default:
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return false;
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}
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}
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static struct tgsi_src_register *
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static struct tgsi_src_register *
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get_tex_coord(struct ir3_compile_context *ctx,
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get_tex_coord(struct ir3_compile_context *ctx,
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struct tgsi_full_instruction *inst,
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struct tgsi_full_instruction *inst,
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@ -1217,8 +1257,8 @@ get_tex_coord(struct ir3_compile_context *ctx,
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if (is_rel_or_const(coord))
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if (is_rel_or_const(coord))
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needs_mov = true;
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needs_mov = true;
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/* 1D textures we fix up w/ 0.0 as 2nd coord: */
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/* 1D textures we fix up w/ 0.5 as 2nd coord: */
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if ((tex == TGSI_TEXTURE_1D) || (tex == TGSI_TEXTURE_SHADOW1D))
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if (is_1d(tex))
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needs_mov = true;
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needs_mov = true;
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/* The texture sample instructions need to coord in successive
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/* The texture sample instructions need to coord in successive
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@ -1252,8 +1292,7 @@ get_tex_coord(struct ir3_compile_context *ctx,
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}
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}
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/* fix up .y coord: */
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/* fix up .y coord: */
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if ((tex == TGSI_TEXTURE_1D) ||
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if (is_1d(tex)) {
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(tex == TGSI_TEXTURE_SHADOW1D)) {
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instr = instr_create(ctx, 1, 0); /* mov */
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instr = instr_create(ctx, 1, 0); /* mov */
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instr->cat1.src_type = type_mov;
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instr->cat1.src_type = type_mov;
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instr->cat1.dst_type = type_mov;
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instr->cat1.dst_type = type_mov;
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