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radeonsi: rename and regroup VS_STATE definitions 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
This commit is contained in:
Marek Olšák 2022-06-06 04:35:40 -04:00 committed by Marge Bot
parent 091617002f
commit c9c7dcb619
6 changed files with 38 additions and 26 deletions
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4
src/gallium/drivers/radeonsi/gfx10_query.c
View File

@ -129,7 +129,7 @@ success:;
sbuf.buffer_offset = qbuf->head;
sbuf.buffer_size = sizeof(struct gfx10_sh_query_buffer_mem);
si_set_internal_shader_buffer(sctx, SI_GS_QUERY_BUF, &sbuf);
sctx->current_vs_state |= S_VS_STATE_STREAMOUT_QUERY_ENABLED(1);
sctx->current_gs_state |= S_GS_STATE_STREAMOUT_QUERY_ENABLED(1);
si_mark_atom_dirty(sctx, &sctx->atoms.s.shader_query);
return true;
@ -185,7 +185,7 @@ static bool gfx10_sh_query_end(struct si_context *sctx, struct si_query *rquery)
if (sctx->num_active_shader_queries <= 0 || !si_is_atom_dirty(sctx, &sctx->atoms.s.shader_query)) {
si_set_internal_shader_buffer(sctx, SI_GS_QUERY_BUF, NULL);
sctx->current_vs_state &= C_VS_STATE_STREAMOUT_QUERY_ENABLED;
sctx->current_gs_state &= C_GS_STATE_STREAMOUT_QUERY_ENABLED;
/* If a query_begin is followed by a query_end without a draw
* in-between, we need to clear the atom to ensure that the

4
src/gallium/drivers/radeonsi/si_query.c
View File

@ -862,7 +862,7 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_h
sbuf.buffer_offset = query->buffer.results_end;
sbuf.buffer_size = buffer->bo_size;
si_set_internal_shader_buffer(sctx, SI_GS_QUERY_EMULATED_COUNTERS_BUF, &sbuf);
sctx->current_gs_state |= S_VS_STATE_GS_PIPELINE_STATS_EMU(1);
sctx->current_gs_state |= S_GS_STATE_PIPELINE_STATS_EMU(1);
const uint32_t zero = 0;
radeon_begin(cs);
@ -976,7 +976,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw
if (--sctx->num_pipeline_stat_emulated_queries == 0) {
si_set_internal_shader_buffer(sctx, SI_GS_QUERY_BUF, NULL);
sctx->current_gs_state &= C_VS_STATE_GS_PIPELINE_STATS_EMU;
sctx->current_gs_state &= C_GS_STATE_PIPELINE_STATS_EMU;
}
} else {
radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0));

2
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -2498,7 +2498,7 @@ bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler
/* Used to export PrimitiveID from the correct vertex. */
shader->key.ge.mono.u.vs_export_prim_id));
shader->uses_vs_state_outprim = sscreen->use_ngg &&
shader->uses_gs_state_outprim = sscreen->use_ngg &&
/* Only used by streamout in vertex shaders. */
sel->stage == MESA_SHADER_VERTEX &&
sel->info.enabled_streamout_buffer_mask;

40
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -251,25 +251,37 @@ enum
SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
};
/* Fields of driver-defined VS state SGPR. */
#define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x)&0x1) << 0)
/* These fields are only set in current_vs_state (except INDEXED) in si_context, and they are
* accessible in the shader via vs_state_bits in all VS, TES, and GS.
*/
#define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x)&0x1) << 0) /* Shared by VS and GS */
#define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE
#define S_VS_STATE_INDEXED(x) (((unsigned)(x)&0x1) << 1)
#define S_VS_STATE_INDEXED(x) (((unsigned)(x)&0x1) << 1) /* Shared by VS and GS */
#define C_VS_STATE_INDEXED 0xFFFFFFFD
#define S_VS_STATE_OUTPRIM(x) (((unsigned)(x)&0x3) << 2)
#define C_VS_STATE_OUTPRIM 0xFFFFFFF3
#define S_VS_STATE_PROVOKING_VTX_INDEX(x) (((unsigned)(x)&0x3) << 4)
#define C_VS_STATE_PROVOKING_VTX_INDEX 0xFFFFFFCF
#define S_VS_STATE_STREAMOUT_QUERY_ENABLED(x) (((unsigned)(x)&0x1) << 6)
#define C_VS_STATE_STREAMOUT_QUERY_ENABLED 0xFFFFFFBF
#define S_VS_STATE_SMALL_PRIM_PRECISION(x) (((unsigned)(x)&0xF) << 7)
#define C_VS_STATE_SMALL_PRIM_PRECISION 0xFFFFF87F
/* These fields are only set in current_vs_state in si_context, and they are accessible
* in the shader via vs_state_bits in LS/HS.
*/
/* bit gap */
#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x)&0x1FFF) << 11)
#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFF0007FF
#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x)&0xFF) << 24)
#define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF
#define S_VS_STATE_GS_PIPELINE_STATS_EMU(x) (((unsigned)(x)&0x1) << 31)
#define C_VS_STATE_GS_PIPELINE_STATS_EMU 0x7FFFFFFF
/* These fields are only set in current_gs_state in si_context, and they are accessible
* in the shader via vs_state_bits in legacy GS, the GS copy shader, and any NGG shader.
*/
#define S_GS_STATE_OUTPRIM(x) (((unsigned)(x)&0x3) << 2)
#define C_GS_STATE_OUTPRIM 0xFFFFFFF3
#define S_GS_STATE_PROVOKING_VTX_INDEX(x) (((unsigned)(x)&0x3) << 4)
#define C_GS_STATE_PROVOKING_VTX_INDEX 0xFFFFFFCF
#define S_GS_STATE_STREAMOUT_QUERY_ENABLED(x) (((unsigned)(x)&0x1) << 6)
#define C_GS_STATE_STREAMOUT_QUERY_ENABLED 0xFFFFFFBF
#define S_GS_STATE_SMALL_PRIM_PRECISION(x) (((unsigned)(x)&0xF) << 7)
#define C_GS_STATE_SMALL_PRIM_PRECISION 0xFFFFF87F
/* bit gap */
#define S_GS_STATE_PIPELINE_STATS_EMU(x) (((unsigned)(x)&0x1) << 31)
#define C_GS_STATE_PIPELINE_STATS_EMU 0x7FFFFFFF
enum
{
@ -836,7 +848,7 @@ struct si_shader {
/* SI_SGPR_VS_STATE_BITS */
bool uses_vs_state_provoking_vertex;
bool uses_vs_state_outprim;
bool uses_gs_state_outprim;
bool uses_base_instance;

10
src/gallium/drivers/radeonsi/si_state_draw.cpp
View File

@ -1211,13 +1211,13 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
if (hw_vs->uses_vs_state_provoking_vertex) {
unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
sctx->current_gs_state &= C_GS_STATE_PROVOKING_VTX_INDEX;
sctx->current_gs_state |= S_GS_STATE_PROVOKING_VTX_INDEX(vtx_index);
}
if (hw_vs->uses_vs_state_outprim) {
sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out_prim);
if (hw_vs->uses_gs_state_outprim) {
sctx->current_gs_state &= C_GS_STATE_OUTPRIM;
sctx->current_gs_state |= S_GS_STATE_OUTPRIM(gs_out_prim);
}
}
}

4
src/gallium/drivers/radeonsi/si_state_viewport.c
View File

@ -141,8 +141,8 @@ static void si_emit_cull_state(struct si_context *sctx)
*
* So pass only the first 4 bits of the float exponent to the shader.
*/
sctx->current_vs_state &= C_VS_STATE_SMALL_PRIM_PRECISION;
sctx->current_vs_state |= S_VS_STATE_SMALL_PRIM_PRECISION(fui(info.small_prim_precision) >> 23);
sctx->current_gs_state &= C_GS_STATE_SMALL_PRIM_PRECISION;
sctx->current_gs_state |= S_GS_STATE_SMALL_PRIM_PRECISION(fui(info.small_prim_precision) >> 23);
}
static void si_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,