i965: Add the new 3DSTATE_PS_BLEND state packet.
v2: Only set GEN8_PS_BLEND_HAS_WRITEABLE_RT if color buffer writes are enabled (caught by Eric Anholt). v3: Set non-blending flags (writeable RT, alpha test, alpha to coverage) for integer formats too. +14 Piglits. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> [v2]
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@ -141,6 +141,7 @@ i965_FILES = \
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gen7_vs_state.c \
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gen7_vs_state.c \
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gen7_wm_state.c \
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gen7_wm_state.c \
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gen7_wm_surface_state.c \
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gen7_wm_surface_state.c \
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gen8_blend_state.c \
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gen8_disasm.c \
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gen8_disasm.c \
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gen8_fs_generator.cpp \
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gen8_fs_generator.cpp \
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gen8_generator.cpp \
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gen8_generator.cpp \
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@ -1673,6 +1673,22 @@ enum brw_message_target {
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# define GEN8_RASTER_SCISSOR_ENABLE (1 << 1)
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# define GEN8_RASTER_SCISSOR_ENABLE (1 << 1)
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# define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0)
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# define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0)
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#define _3DSTATE_PS_BLEND 0x784D /* GEN8+ */
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/* DW1 */
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# define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31)
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# define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30)
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# define GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE (1 << 29)
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# define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(28, 24)
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# define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT 24
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# define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(23, 19)
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# define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT 19
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# define GEN8_PS_BLEND_SRC_BLEND_FACTOR_MASK INTEL_MASK(18, 14)
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# define GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT 14
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# define GEN8_PS_BLEND_DST_BLEND_FACTOR_MASK INTEL_MASK(13, 9)
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# define GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT 9
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# define GEN8_PS_BLEND_ALPHA_TEST_ENABLE (1 << 8)
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# define GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE (1 << 7)
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#define _3DSTATE_WM_DEPTH_STENCIL 0x784E /* GEN8+ */
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#define _3DSTATE_WM_DEPTH_STENCIL 0x784E /* GEN8+ */
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/* DW1 */
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/* DW1 */
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# define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT 29
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# define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT 29
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@ -131,6 +131,7 @@ extern const struct brw_tracked_state gen7_urb;
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extern const struct brw_tracked_state gen7_vs_state;
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extern const struct brw_tracked_state gen7_vs_state;
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extern const struct brw_tracked_state gen7_wm_state;
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extern const struct brw_tracked_state gen7_wm_state;
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extern const struct brw_tracked_state haswell_cut_index;
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extern const struct brw_tracked_state haswell_cut_index;
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extern const struct brw_tracked_state gen8_ps_blend;
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extern const struct brw_tracked_state gen8_wm_depth_stencil;
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extern const struct brw_tracked_state gen8_wm_depth_stencil;
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extern const struct brw_tracked_state gen8_raster_state;
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extern const struct brw_tracked_state gen8_raster_state;
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extern const struct brw_tracked_state gen8_sbe_state;
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extern const struct brw_tracked_state gen8_sbe_state;
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@ -304,6 +304,7 @@ static const struct brw_tracked_state *gen8_atoms[] =
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&gen8_raster_state,
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&gen8_raster_state,
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&gen8_sbe_state,
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&gen8_sbe_state,
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&gen8_sf_state,
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&gen8_sf_state,
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&gen8_ps_blend,
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&gen8_wm_depth_stencil,
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&gen8_wm_depth_stencil,
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&gen7_wm_state,
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&gen7_wm_state,
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&gen7_ps_state,
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&gen7_ps_state,
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@ -0,0 +1,123 @@
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_context.h"
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#include "brw_state.h"
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#include "brw_defines.h"
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#include "brw_util.h"
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#include "brw_wm.h"
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#include "intel_batchbuffer.h"
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#include "main/macros.h"
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#include "main/enums.h"
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#include "main/glformats.h"
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#define blend_factor(x) brw_translate_blend_factor(x)
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static void
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gen8_upload_ps_blend(struct brw_context *brw)
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{
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struct gl_context *ctx = &brw->ctx;
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uint32_t dw1 = 0;
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/* _NEW_BUFFERS */
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struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
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if (brw_color_buffer_write_enabled(brw))
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dw1 |= GEN8_PS_BLEND_HAS_WRITEABLE_RT;
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/* _NEW_COLOR */
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if (ctx->Color.AlphaEnabled)
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dw1 |= GEN8_PS_BLEND_ALPHA_TEST_ENABLE;
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/* _NEW_MULTISAMPLE */
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if (ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToCoverage)
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dw1 |= GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE;
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/* Used for implementing the following bit of GL_EXT_texture_integer:
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* "Per-fragment operations that require floating-point color
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* components, including multisample alpha operations, alpha test,
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* blending, and dithering, have no effect when the corresponding
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* colors are written to an integer color buffer."
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*
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* The OpenGL specification 3.3 (page 196), section 4.1.3 says:
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* "If drawbuffer zero is not NONE and the buffer it references has an
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* integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
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* operations are skipped."
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*/
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GLenum rb_type =
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rb ? _mesa_get_format_datatype(rb->Format) : GL_UNSIGNED_NORMALIZED;
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if (rb && rb_type != GL_INT && rb_type != GL_UNSIGNED_INT &&
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(ctx->Color.BlendEnabled & 1)) {
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GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
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GLenum eqA = ctx->Color.Blend[0].EquationA;
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GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
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GLenum dstRGB = ctx->Color.Blend[0].DstRGB;
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GLenum srcA = ctx->Color.Blend[0].SrcA;
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GLenum dstA = ctx->Color.Blend[0].DstA;
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if (eqRGB == GL_MIN || eqRGB == GL_MAX)
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srcRGB = dstRGB = GL_ONE;
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if (eqA == GL_MIN || eqA == GL_MAX)
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srcA = dstA = GL_ONE;
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/* Due to hardware limitations, the destination may have information
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* in an alpha channel even when the format specifies no alpha
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* channel. In order to avoid getting any incorrect blending due to
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* that alpha channel, coerce the blend factors to values that will
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* not read the alpha channel, but will instead use the correct
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* implicit value for alpha.
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*/
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if (!_mesa_base_format_has_channel(rb->_BaseFormat, GL_TEXTURE_ALPHA_TYPE)) {
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srcRGB = brw_fix_xRGB_alpha(srcRGB);
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srcA = brw_fix_xRGB_alpha(srcA);
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dstRGB = brw_fix_xRGB_alpha(dstRGB);
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dstA = brw_fix_xRGB_alpha(dstA);
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}
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dw1 |=
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GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE |
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SET_FIELD(blend_factor(dstRGB), GEN8_PS_BLEND_DST_BLEND_FACTOR) |
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SET_FIELD(blend_factor(srcRGB), GEN8_PS_BLEND_SRC_BLEND_FACTOR) |
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SET_FIELD(blend_factor(dstA), GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR) |
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SET_FIELD(blend_factor(srcA), GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR);
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if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
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dw1 |= GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE;
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}
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BEGIN_BATCH(2);
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OUT_BATCH(_3DSTATE_PS_BLEND << 16 | (2 - 2));
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OUT_BATCH(dw1);
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ADVANCE_BATCH();
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}
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const struct brw_tracked_state gen8_ps_blend = {
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.dirty = {
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.mesa = _NEW_BUFFERS | _NEW_COLOR | _NEW_MULTISAMPLE,
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.brw = BRW_NEW_CONTEXT,
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.cache = 0,
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},
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.emit = gen8_upload_ps_blend
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};
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