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radv/gfx10: mask DCC tile swizzle by alignment 

DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-06-25 14:28:10 +02:00 committed by Bas Nieuwenhuizen
parent b1b60a92b1
commit c90f46700d
1 changed files with 4 additions and 1 deletions
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5
src/amd/vulkan/radv_device.c
View File

@ -4423,8 +4423,11 @@ radv_initialise_color_surface(struct radv_device *device,
device->physical_device->rad_info.chip_class <= GFX8)
va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
unsigned dcc_tile_swizzle = surf->tile_swizzle;
dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
cb->cb_dcc_base = va >> 8;
cb->cb_dcc_base |= surf->tile_swizzle;
cb->cb_dcc_base |= dcc_tile_swizzle;
/* GFX10 field has the same base shift as the GFX6 field. */
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;