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intel/compiler: Fix src0/desc setter ordering 

src0 vstride and type overlap with bits of the extended descriptor.
brw_set_desc() also sets the extended descriptor to 0.  So by setting
the descriptor, then setting src0, we were accidentally setting a bunch
of extended descriptor bits unintentionally.

When using this infrastructure for framebuffer writes (in a future
patch), this ended up setting the extended descriptor bit 20, which is
"Null Render Target" on Icelake, causing nothing to be written to the
framebuffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke 2019-08-26 15:21:40 -07:00
parent 360cf3c4b0
commit c8c9c48684
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_eu_emit.c
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@ -2525,8 +2525,8 @@ brw_send_indirect_message(struct brw_codegen *p,
if (desc.file == BRW_IMMEDIATE_VALUE) {
send = next_insn(p, BRW_OPCODE_SEND);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_desc(p, send, desc.ud | desc_imm);
} else {
struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
@ -2545,11 +2545,11 @@ brw_send_indirect_message(struct brw_codegen *p,
brw_pop_insn_state(p);
send = next_insn(p, BRW_OPCODE_SEND);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_src1(p, send, addr);
}
brw_set_dest(p, send, dst);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_inst_set_sfid(devinfo, send, sfid);
brw_inst_set_eot(devinfo, send, eot);
}