i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation change in the surrounding code removing tabs. v2 (Matt): Fixed whitespace: tabs -> spaces Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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@ -967,10 +967,10 @@ struct brw_context
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unsigned unit,
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uint32_t *surf_offset,
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bool for_gather);
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void (*update_renderbuffer_surface)(struct brw_context *brw,
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struct gl_renderbuffer *rb,
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bool layered,
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unsigned unit);
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uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
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struct gl_renderbuffer *rb,
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bool layered, unsigned unit,
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uint32_t surf_index);
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void (*emit_texture_surface_state)(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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@ -626,11 +626,11 @@ brw_emit_null_surface_state(struct brw_context *brw,
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* While it is only used for the front/back buffer currently, it should be
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* usable for further buffers when doing ARB_draw_buffer support.
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*/
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static void
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static uint32_t
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brw_update_renderbuffer_surface(struct brw_context *brw,
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struct gl_renderbuffer *rb,
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bool layered,
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unsigned int unit)
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struct gl_renderbuffer *rb,
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bool layered, unsigned unit,
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uint32_t surf_index)
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{
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struct gl_context *ctx = &brw->ctx;
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struct intel_renderbuffer *irb = intel_renderbuffer(rb);
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@ -638,11 +638,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
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uint32_t *surf;
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uint32_t tile_x, tile_y;
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uint32_t format = 0;
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uint32_t offset;
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/* _NEW_BUFFERS */
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mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
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/* BRW_NEW_FS_PROG_DATA */
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uint32_t surf_index =
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brw->wm.prog_data->binding_table.render_target_start + unit;
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assert(!layered);
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@ -663,8 +662,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
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intel_miptree_used_for_rendering(irb->mt);
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surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
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&brw->wm.base.surf_offset[surf_index]);
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surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
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format = brw->render_target_format[rb_format];
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if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
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@ -721,11 +719,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
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}
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drm_intel_bo_emit_reloc(brw->batch.bo,
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brw->wm.base.surf_offset[surf_index] + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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offset + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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return offset;
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}
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/**
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@ -743,13 +743,15 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
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/* Update surfaces for drawing buffers */
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if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
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for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
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if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
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brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
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ctx->DrawBuffer->MaxNumLayers > 0, i);
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} else {
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const uint32_t surf_index =
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brw->wm.prog_data->binding_table.render_target_start + i;
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const uint32_t surf_index =
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brw->wm.prog_data->binding_table.render_target_start + i;
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if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
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brw->wm.base.surf_offset[surf_index] =
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brw->vtbl.update_renderbuffer_surface(
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brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
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ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index);
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} else {
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brw->vtbl.emit_null_surface_state(
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brw, fb->Width, fb->Height, fb->Visual.samples,
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&brw->wm.base.surf_offset[surf_index]);
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@ -45,17 +45,18 @@
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* While it is only used for the front/back buffer currently, it should be
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* usable for further buffers when doing ARB_draw_buffer support.
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*/
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static void
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static uint32_t
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gen6_update_renderbuffer_surface(struct brw_context *brw,
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struct gl_renderbuffer *rb,
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bool layered,
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unsigned int unit)
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bool layered, unsigned unit /* unused */,
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uint32_t surf_index)
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{
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struct gl_context *ctx = &brw->ctx;
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struct intel_renderbuffer *irb = intel_renderbuffer(rb);
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struct intel_mipmap_tree *mt = irb->mt;
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uint32_t *surf;
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uint32_t format = 0;
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uint32_t offset;
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/* _NEW_BUFFERS */
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mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
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uint32_t surftype;
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@ -63,13 +64,9 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
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const GLenum gl_target =
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rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
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uint32_t surf_index =
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brw->wm.prog_data->binding_table.render_target_start + unit;
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intel_miptree_used_for_rendering(irb->mt);
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surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
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&brw->wm.base.surf_offset[surf_index]);
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surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
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format = brw->render_target_format[rb_format];
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if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
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@ -131,11 +128,13 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
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surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
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drm_intel_bo_emit_reloc(brw->batch.bo,
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brw->wm.base.surf_offset[surf_index] + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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offset + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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return offset;
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}
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void
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@ -448,11 +448,11 @@ gen7_emit_null_surface_state(struct brw_context *brw,
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* While it is only used for the front/back buffer currently, it should be
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* usable for further buffers when doing ARB_draw_buffer support.
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*/
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static void
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static uint32_t
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gen7_update_renderbuffer_surface(struct brw_context *brw,
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struct gl_renderbuffer *rb,
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bool layered,
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unsigned int unit)
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struct gl_renderbuffer *rb,
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bool layered, unsigned unit /* unused */,
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uint32_t surf_index)
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{
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struct gl_context *ctx = &brw->ctx;
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struct intel_renderbuffer *irb = intel_renderbuffer(rb);
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@ -464,17 +464,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
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bool is_array = false;
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int depth = MAX2(irb->layer_count, 1);
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const uint8_t mocs = GEN7_MOCS_L3;
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uint32_t offset;
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int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1);
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GLenum gl_target = rb->TexImage ?
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rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
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uint32_t surf_index =
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brw->wm.prog_data->binding_table.render_target_start + unit;
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uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32,
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&brw->wm.base.surf_offset[surf_index]);
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&offset);
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memset(surf, 0, 8 * 4);
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intel_miptree_used_for_rendering(irb->mt);
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@ -539,7 +537,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
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(depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
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if (irb->mt->mcs_mt) {
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gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index],
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gen7_set_surface_mcs_info(brw, surf, offset,
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irb->mt->mcs_mt, true /* is RT */);
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}
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@ -553,13 +551,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
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}
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drm_intel_bo_emit_reloc(brw->batch.bo,
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brw->wm.base.surf_offset[surf_index] + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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offset + 4,
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mt->bo,
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surf[1] - mt->bo->offset64,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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gen7_check_surface_setup(surf, true /* is_render_target */);
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return offset;
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}
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void
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@ -324,11 +324,11 @@ gen8_emit_null_surface_state(struct brw_context *brw,
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* While it is only used for the front/back buffer currently, it should be
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* usable for further buffers when doing ARB_draw_buffer support.
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*/
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static void
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static uint32_t
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gen8_update_renderbuffer_surface(struct brw_context *brw,
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struct gl_renderbuffer *rb,
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bool layered,
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unsigned unit)
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bool layered, unsigned unit /* unused */,
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uint32_t surf_index)
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{
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struct gl_context *ctx = &brw->ctx;
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struct intel_renderbuffer *irb = intel_renderbuffer(rb);
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@ -341,14 +341,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
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uint32_t tiling = mt->tiling;
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uint32_t format = 0;
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uint32_t surf_type;
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uint32_t offset;
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bool is_array = false;
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int depth = MAX2(irb->layer_count, 1);
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const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ?
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irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1));
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GLenum gl_target =
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rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
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uint32_t surf_index =
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brw->wm.prog_data->binding_table.render_target_start + unit;
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/* FINISHME: Use PTE MOCS on Skylake. */
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uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE;
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@ -393,8 +392,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
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aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
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}
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uint32_t *surf =
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allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]);
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uint32_t *surf = allocate_surface_state(brw, &offset);
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surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
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(is_array ? GEN7_SURFACE_IS_ARRAY : 0) |
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@ -439,7 +437,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
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if (aux_mt) {
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*((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
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drm_intel_bo_emit_reloc(brw->batch.bo,
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brw->wm.base.surf_offset[surf_index] + 10 * 4,
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offset + 10 * 4,
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aux_mt->bo, 0,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
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} else {
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@ -449,11 +447,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
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surf[12] = 0;
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drm_intel_bo_emit_reloc(brw->batch.bo,
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brw->wm.base.surf_offset[surf_index] + 8 * 4,
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offset + 8 * 4,
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mt->bo,
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mt->offset,
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I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER);
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return offset;
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}
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void
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