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i965/drm: Make alignment parameter a uint64_t. 

Theoretically, with a 48-bit address space, we could have buffers
with an alignment of >= 4GB.  It's a bit silly, but the exec_object
structs (drm_i915_gem_exec_object2) use a __u64 for this, so we may
as well use the same type as the kernel API.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Kenneth Graunke 2017-04-10 23:55:21 -07:00
parent 444ab8126d
commit c85d6832fd
2 changed files with 4 additions and 4 deletions
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4
src/mesa/drivers/dri/i965/brw_bufmgr.c
View File

@ -247,7 +247,7 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
unsigned long size,
unsigned long flags,
uint32_t tiling_mode,
uint32_t stride, unsigned int alignment)
uint32_t stride, uint64_t alignment)
{
struct brw_bo *bo;
unsigned int page_size = getpagesize();
@ -369,7 +369,7 @@ err:
struct brw_bo *
brw_bo_alloc(struct brw_bufmgr *bufmgr,
const char *name, unsigned long size, unsigned int alignment)
const char *name, unsigned long size, uint64_t alignment)
{
return bo_alloc_internal(bufmgr, name, size, 0, I915_TILING_NONE, 0, 0);
}

4
src/mesa/drivers/dri/i965/brw_bufmgr.h
View File

@ -60,7 +60,7 @@ struct brw_bo {
*
* Used for GTT mapping & pinning the object.
*/
unsigned long align;
uint64_t align;
/**
* Virtual address for accessing the buffer data. Only valid while
@ -140,7 +140,7 @@ struct brw_bo {
* using bo_map() or brw_bo_map_gtt() to be used by the CPU.
*/
struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
unsigned long size, unsigned int alignment);
unsigned long size, uint64_t alignment);
/**
* Allocate a tiled buffer object.