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intel/nir: Allow splitting a single load into up to 32 loads 

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
This commit is contained in:
Jason Ekstrand 2020-08-20 23:59:54 -05:00 committed by Marge Bot
parent febe762246
commit c84e2784eb
1 changed files with 4 additions and 2 deletions
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6
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c
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@ -109,8 +109,10 @@ lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
result = nir_extract_bits(b, &load, 1, load_offset * 8,
num_components, bit_size);
} else {
/* Otherwise, we have to break it into smaller loads */
nir_ssa_def *loads[8];
/* Otherwise, we have to break it into smaller loads. We could end up
* with as many as 32 loads if we're loading a u64vec16 from scratch.
*/
nir_ssa_def *loads[32];
unsigned num_loads = 0;
int load_offset = 0;
while (load_offset < bytes_read) {