intel/fs/gen12: Add tests for scoreboard pass
Tests the combinations of cases of RAW, WAW and WAR hazards involving both inorder and outoforder instructions. Also tests that dependencies combine and propagate correctly through control flow (loops and conditionals). v2: Add an extra test illustrating that the non-logical CFG edge between then-block and else-block is being taking into account. (Curro) Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
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@ -148,7 +148,7 @@ if with_tests
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'fs_saturate_propagation', 'vf_float_conversions',
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'vec4_register_coalesce', 'vec4_copy_propagation',
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'vec4_cmod_propagation', 'vec4_dead_code_eliminate',
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'eu_compact', 'eu_validate']
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'eu_compact', 'eu_validate', 'fs_scoreboard']
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test(
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t,
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executable(
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@ -0,0 +1,863 @@
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/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <gtest/gtest.h>
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#include "brw_fs.h"
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#include "brw_cfg.h"
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#include "program/program.h"
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using namespace brw;
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class scoreboard_test : public ::testing::Test {
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virtual void SetUp();
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public:
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struct brw_compiler *compiler;
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struct gen_device_info *devinfo;
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struct gl_context *ctx;
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struct brw_wm_prog_data *prog_data;
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struct gl_shader_program *shader_prog;
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fs_visitor *v;
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};
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void scoreboard_test::SetUp()
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{
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ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
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compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
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devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
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compiler->devinfo = devinfo;
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prog_data = ralloc(NULL, struct brw_wm_prog_data);
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nir_shader *shader =
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nir_shader_create(NULL, MESA_SHADER_FRAGMENT, NULL, NULL);
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v = new fs_visitor(compiler, NULL, NULL, NULL, &prog_data->base, shader, 8, -1);
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devinfo->gen = 12;
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}
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static fs_inst *
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instruction(bblock_t *block, int num)
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{
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fs_inst *inst = (fs_inst *)block->start();
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for (int i = 0; i < num; i++) {
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inst = (fs_inst *)inst->next;
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}
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return inst;
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}
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static void
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lower_scoreboard(fs_visitor *v)
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{
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const bool print = getenv("TEST_DEBUG");
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if (print) {
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fprintf(stderr, "= Before =\n");
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v->cfg->dump(v);
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}
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v->lower_scoreboard();
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if (print) {
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fprintf(stderr, "\n= After =\n");
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v->cfg->dump(v);
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}
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}
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fs_inst *
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emit_SEND(const fs_builder &bld, const fs_reg &dst,
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const fs_reg &desc, const fs_reg &payload)
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{
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fs_inst *inst = bld.emit(SHADER_OPCODE_SEND, dst, desc, desc, payload);
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inst->mlen = 1;
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return inst;
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}
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bool operator ==(const tgl_swsb &a, const tgl_swsb &b)
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{
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return a.mode == b.mode &&
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a.regdist == b.regdist &&
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(a.mode == TGL_SBID_NULL || a.sbid == b.sbid);
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}
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std::ostream &operator<<(std::ostream &os, const tgl_swsb &swsb) {
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if (swsb.regdist)
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os << "@" << swsb.regdist;
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if (swsb.mode) {
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if (swsb.regdist)
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os << " ";
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os << "$" << swsb.sbid;
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if (swsb.mode & TGL_SBID_DST)
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os << ".dst";
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if (swsb.mode & TGL_SBID_SRC)
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os << ".src";
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}
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return os;
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}
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TEST_F(scoreboard_test, RAW_inorder_inorder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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fs_reg y = v->vgrf(glsl_type::int_type);
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bld.ADD( x, g[1], g[2]);
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bld.MUL( y, g[3], g[4]);
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bld.AND(g[5], x, y);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_regdist(1));
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}
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TEST_F(scoreboard_test, RAW_inorder_outoforder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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bld.ADD( x, g[1], g[2]);
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bld.MUL( g[3], g[4], g[5]);
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emit_SEND(bld, g[6], g[7], x);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched,
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(tgl_swsb { .regdist = 2, .sbid = 0, .mode = TGL_SBID_SET }));
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}
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TEST_F(scoreboard_test, RAW_outoforder_inorder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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fs_reg y = v->vgrf(glsl_type::int_type);
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emit_SEND(bld, x, g[1], g[2]);
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bld.MUL( y, g[3], g[4]);
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bld.AND( g[5], x, y);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0));
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched,
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(tgl_swsb { .regdist = 1, .sbid = 0, .mode = TGL_SBID_DST }));
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}
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TEST_F(scoreboard_test, RAW_outoforder_outoforder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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/* The second SEND depends on the first, and would need to refer to two
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* SBIDs. Since it is not possible we expect a SYNC instruction to be
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* added.
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*/
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fs_reg x = v->vgrf(glsl_type::int_type);
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emit_SEND(bld, x, g[1], g[2]);
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emit_SEND(bld, g[3], x, g[4])->sfid++;
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(1, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0));
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fs_inst *sync = instruction(block0, 1);
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EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC);
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EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0));
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EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SET, 1));
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}
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TEST_F(scoreboard_test, WAR_inorder_inorder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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bld.ADD(g[1], x, g[2]);
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bld.MUL(g[3], g[4], g[5]);
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bld.AND( x, g[6], g[7]);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_null());
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}
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TEST_F(scoreboard_test, WAR_inorder_outoforder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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bld.ADD( g[1], x, g[2]);
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bld.MUL( g[3], g[4], g[5]);
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emit_SEND(bld, x, g[6], g[7]);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched,
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(tgl_swsb { .regdist = 2, .sbid = 0, .mode = TGL_SBID_SET }));
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}
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TEST_F(scoreboard_test, WAR_outoforder_inorder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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emit_SEND(bld, g[1], g[2], x);
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bld.MUL( g[4], g[5], g[6]);
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bld.AND( x, g[7], g[8]);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0));
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SRC, 0));
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}
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TEST_F(scoreboard_test, WAR_outoforder_outoforder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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emit_SEND(bld, g[1], g[2], x);
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emit_SEND(bld, x, g[3], g[4])->sfid++;
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(1, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0));
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fs_inst *sync = instruction(block0, 1);
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EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC);
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EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_SRC, 0));
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EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SET, 1));
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}
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TEST_F(scoreboard_test, WAW_inorder_inorder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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bld.ADD( x, g[1], g[2]);
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bld.MUL(g[3], g[4], g[5]);
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bld.AND( x, g[6], g[7]);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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/* NOTE: We only need this RegDist if a long instruction is followed by a
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* short one. The pass is currently conservative about this and adding the
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* annotation.
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*/
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EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_regdist(2));
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}
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TEST_F(scoreboard_test, WAW_inorder_outoforder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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fs_reg x = v->vgrf(glsl_type::int_type);
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bld.ADD( x, g[1], g[2]);
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bld.MUL( g[3], g[4], g[5]);
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emit_SEND(bld, x, g[6], g[7]);
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v->calculate_cfg();
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bblock_t *block0 = v->cfg->blocks[0];
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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lower_scoreboard(v);
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ASSERT_EQ(0, block0->start_ip);
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ASSERT_EQ(2, block0->end_ip);
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EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
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EXPECT_EQ(instruction(block0, 2)->sched,
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(tgl_swsb { .regdist = 2, .sbid = 0, .mode = TGL_SBID_SET }));
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}
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TEST_F(scoreboard_test, WAW_outoforder_inorder)
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{
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const fs_builder &bld = v->bld;
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fs_reg g[16];
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for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
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g[i] = v->vgrf(glsl_type::int_type);
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||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
emit_SEND(bld, x, g[1], g[2]);
|
||||
bld.MUL( g[3], g[4], g[5]);
|
||||
bld.AND( x, g[6], g[7]);
|
||||
|
||||
v->calculate_cfg();
|
||||
bblock_t *block0 = v->cfg->blocks[0];
|
||||
ASSERT_EQ(0, block0->start_ip);
|
||||
ASSERT_EQ(2, block0->end_ip);
|
||||
|
||||
lower_scoreboard(v);
|
||||
ASSERT_EQ(0, block0->start_ip);
|
||||
ASSERT_EQ(2, block0->end_ip);
|
||||
|
||||
EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0));
|
||||
EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null());
|
||||
EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_DST, 0));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, WAW_outoforder_outoforder)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
emit_SEND(bld, x, g[1], g[2]);
|
||||
emit_SEND(bld, x, g[3], g[4])->sfid++;
|
||||
|
||||
v->calculate_cfg();
|
||||
bblock_t *block0 = v->cfg->blocks[0];
|
||||
ASSERT_EQ(0, block0->start_ip);
|
||||
ASSERT_EQ(1, block0->end_ip);
|
||||
|
||||
lower_scoreboard(v);
|
||||
ASSERT_EQ(0, block0->start_ip);
|
||||
ASSERT_EQ(2, block0->end_ip);
|
||||
|
||||
EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0));
|
||||
|
||||
fs_inst *sync = instruction(block0, 1);
|
||||
EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC);
|
||||
EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0));
|
||||
|
||||
EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SET, 1));
|
||||
}
|
||||
|
||||
|
||||
TEST_F(scoreboard_test, loop1)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_DO);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_WHILE)->predicate = BRW_PREDICATE_NORMAL;
|
||||
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *body = v->cfg->blocks[2];
|
||||
fs_inst *add = instruction(body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(1));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 0);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(1));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, loop2)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_DO);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_WHILE)->predicate = BRW_PREDICATE_NORMAL;
|
||||
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
/* Now the write in ADD has the tightest RegDist for both ADD and MUL. */
|
||||
|
||||
bblock_t *body = v->cfg->blocks[2];
|
||||
fs_inst *add = instruction(body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 0);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, loop3)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_DO);
|
||||
|
||||
/* For the ADD in the loop body this extra distance will always apply. */
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
bld.XOR(g[6], g[1], g[2]);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_WHILE)->predicate = BRW_PREDICATE_NORMAL;
|
||||
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *body = v->cfg->blocks[2];
|
||||
fs_inst *add = instruction(body, 4);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(5));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 0);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(1));
|
||||
}
|
||||
|
||||
|
||||
TEST_F(scoreboard_test, conditional1)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[2];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional2)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(5));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[2];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional3)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(body, 3);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(5));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[2];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional4)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[2];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(3));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional5)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_ELSE);
|
||||
|
||||
bld.ROL( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *then_body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(then_body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *else_body = v->cfg->blocks[2];
|
||||
fs_inst *rol = instruction(else_body, 0);
|
||||
EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL);
|
||||
EXPECT_EQ(rol->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional6)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_ELSE);
|
||||
|
||||
bld.XOR(g[6], g[1], g[2]);
|
||||
bld.XOR(g[7], g[1], g[2]);
|
||||
bld.XOR(g[8], g[1], g[2]);
|
||||
bld.XOR(g[9], g[1], g[2]);
|
||||
bld.ROL( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *then_body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(then_body, 3);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(5));
|
||||
|
||||
bblock_t *else_body = v->cfg->blocks[2];
|
||||
fs_inst *rol = instruction(else_body, 4);
|
||||
EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL);
|
||||
EXPECT_EQ(rol->sched, tgl_swsb_regdist(6));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional7)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_ELSE);
|
||||
|
||||
bld.ROL( x, g[1], g[2]);
|
||||
bld.XOR(g[6], g[1], g[2]);
|
||||
bld.XOR(g[7], g[1], g[2]);
|
||||
bld.XOR(g[8], g[1], g[2]);
|
||||
bld.XOR(g[9], g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *then_body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(then_body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *else_body = v->cfg->blocks[2];
|
||||
fs_inst *rol = instruction(else_body, 0);
|
||||
EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL);
|
||||
EXPECT_EQ(rol->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(6));
|
||||
}
|
||||
|
||||
TEST_F(scoreboard_test, conditional8)
|
||||
{
|
||||
const fs_builder &bld = v->bld;
|
||||
fs_reg g[16];
|
||||
for (unsigned i = 0; i < ARRAY_SIZE(g); i++)
|
||||
g[i] = v->vgrf(glsl_type::int_type);
|
||||
|
||||
fs_reg x = v->vgrf(glsl_type::int_type);
|
||||
bld.XOR( x, g[1], g[2]);
|
||||
bld.XOR(g[3], g[1], g[2]);
|
||||
bld.XOR(g[4], g[1], g[2]);
|
||||
bld.XOR(g[5], g[1], g[2]);
|
||||
bld.XOR(g[6], g[1], g[2]);
|
||||
bld.XOR(g[7], g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_IF);
|
||||
|
||||
bld.ADD( x, g[1], g[2]);
|
||||
bld.emit(BRW_OPCODE_ELSE);
|
||||
|
||||
bld.ROL( x, g[1], g[2]);
|
||||
|
||||
bld.emit(BRW_OPCODE_ENDIF);
|
||||
bld.MUL( x, g[1], g[2]);
|
||||
|
||||
v->calculate_cfg();
|
||||
lower_scoreboard(v);
|
||||
|
||||
bblock_t *then_body = v->cfg->blocks[1];
|
||||
fs_inst *add = instruction(then_body, 0);
|
||||
EXPECT_EQ(add->opcode, BRW_OPCODE_ADD);
|
||||
EXPECT_EQ(add->sched, tgl_swsb_regdist(7));
|
||||
|
||||
/* Note that the ROL will have RegDist 2 and not 7, illustrating the
|
||||
* physical CFG edge between the then-block and the else-block.
|
||||
*/
|
||||
bblock_t *else_body = v->cfg->blocks[2];
|
||||
fs_inst *rol = instruction(else_body, 0);
|
||||
EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL);
|
||||
EXPECT_EQ(rol->sched, tgl_swsb_regdist(2));
|
||||
|
||||
bblock_t *last_block = v->cfg->blocks[3];
|
||||
fs_inst *mul = instruction(last_block, 1);
|
||||
EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL);
|
||||
EXPECT_EQ(mul->sched, tgl_swsb_regdist(2));
|
||||
}
|
Loading…
Reference in New Issue