freedreno/ir3: split out delay helpers
We're going to want these also for a post-RA sched pass. And also to split nop stuffing out into it's own pass. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3569>
This commit is contained in:
parent
54c795f829
commit
c803c662f9
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@ -1113,10 +1113,16 @@ static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
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void ir3_print(struct ir3 *ir);
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void ir3_print_instr(struct ir3_instruction *instr);
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/* depth calculation: */
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struct ir3_shader_variant;
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/* delay calculation: */
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int ir3_delayslots(struct ir3_instruction *assigner,
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struct ir3_instruction *consumer, unsigned n);
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unsigned ir3_distance(struct ir3_block *block, struct ir3_instruction *instr,
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unsigned maxd, bool pred);
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unsigned ir3_delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
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bool soft, bool pred);
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/* depth calculation: */
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struct ir3_shader_variant;
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void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
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void ir3_depth(struct ir3 *ir, struct ir3_shader_variant *so);
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@ -0,0 +1,337 @@
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/*
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* Copyright (C) 2019 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include "ir3.h"
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/*
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* Helpers to figure out the necessary delay slots between instructions. Used
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* both in scheduling pass(es) and the final pass to insert any required nop's
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* so that the shader program is valid.
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*
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* Note that this needs to work both pre and post RA, so we can't assume ssa
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* src iterators work.
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*/
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/* generally don't count false dependencies, since this can just be
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* something like a barrier, or SSBO store. The exception is array
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* dependencies if the assigner is an array write and the consumer
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* reads the same array.
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*/
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static bool
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ignore_dep(struct ir3_instruction *assigner,
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struct ir3_instruction *consumer, unsigned n)
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{
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if (!__is_false_dep(consumer, n))
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return false;
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if (assigner->barrier_class & IR3_BARRIER_ARRAY_W) {
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struct ir3_register *dst = assigner->regs[0];
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struct ir3_register *src;
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debug_assert(dst->flags & IR3_REG_ARRAY);
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foreach_src (src, consumer) {
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if ((src->flags & IR3_REG_ARRAY) &&
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(dst->array.id == src->array.id)) {
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return false;
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}
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}
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}
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return true;
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}
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/* calculate required # of delay slots between the instruction that
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* assigns a value and the one that consumes
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*/
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int
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ir3_delayslots(struct ir3_instruction *assigner,
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struct ir3_instruction *consumer, unsigned n)
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{
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if (ignore_dep(assigner, consumer, n))
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return 0;
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/* worst case is cat1-3 (alu) -> cat4/5 needing 6 cycles, normal
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* alu -> alu needs 3 cycles, cat4 -> alu and texture fetch
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* handled with sync bits
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*/
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if (is_meta(assigner) || is_meta(consumer))
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return 0;
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if (writes_addr(assigner))
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return 6;
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/* handled via sync flags: */
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if (is_sfu(assigner) || is_tex(assigner) || is_mem(assigner))
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return 0;
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/* assigner must be alu: */
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if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer) ||
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is_mem(consumer)) {
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return 6;
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} else if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
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(n == 3)) {
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/* special case, 3rd src to cat3 not required on first cycle */
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return 1;
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} else {
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return 3;
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}
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}
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static bool
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count_instruction(struct ir3_instruction *n)
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{
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/* NOTE: don't count branch/jump since we don't know yet if they will
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* be eliminated later in resolve_jumps().. really should do that
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* earlier so we don't have this constraint.
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*/
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return is_alu(n) || (is_flow(n) && (n->opc != OPC_JUMP) && (n->opc != OPC_BR));
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}
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/**
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* @block: the block to search in, starting from end; in first pass,
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* this will be the block the instruction would be inserted into
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* (but has not yet, ie. it only contains already scheduled
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* instructions). For intra-block scheduling (second pass), this
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* would be one of the predecessor blocks.
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* @instr: the instruction to search for
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* @maxd: max distance, bail after searching this # of instruction
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* slots, since it means the instruction we are looking for is
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* far enough away
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* @pred: if true, recursively search into predecessor blocks to
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* find the worst case (shortest) distance (only possible after
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* individual blocks are all scheduled)
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*/
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unsigned
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ir3_distance(struct ir3_block *block, struct ir3_instruction *instr,
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unsigned maxd, bool pred)
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{
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unsigned d = 0;
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/* Note that this relies on incrementally building up the block's
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* instruction list.. but this is how scheduling and nopsched
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* work.
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*/
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foreach_instr_rev (n, &block->instr_list) {
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if ((n == instr) || (d >= maxd))
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return MIN2(maxd, d + n->nop);
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if (count_instruction(n))
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d = MIN2(maxd, d + 1 + n->repeat + n->nop);
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}
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/* if coming from a predecessor block, assume it is assigned far
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* enough away.. we'll fix up later.
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*/
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if (!pred)
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return maxd;
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if (pred && (block->data != block)) {
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/* Search into predecessor blocks, finding the one with the
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* shortest distance, since that will be the worst case
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*/
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unsigned min = maxd - d;
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/* (ab)use block->data to prevent recursion: */
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block->data = block;
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set_foreach (block->predecessors, entry) {
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struct ir3_block *pred = (struct ir3_block *)entry->key;
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unsigned n;
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n = ir3_distance(pred, instr, min, pred);
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min = MIN2(min, n);
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}
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block->data = NULL;
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d += min;
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}
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return d;
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}
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/* calculate delay for specified src: */
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static unsigned
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delay_calc_srcn(struct ir3_block *block,
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struct ir3_instruction *assigner,
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struct ir3_instruction *consumer,
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unsigned srcn, bool soft, bool pred)
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{
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unsigned delay = 0;
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if (is_meta(assigner)) {
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struct ir3_register *src;
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foreach_src (src, assigner) {
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unsigned d;
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if (!src->instr)
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continue;
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d = delay_calc_srcn(block, src->instr, consumer, srcn, soft, pred);
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delay = MAX2(delay, d);
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}
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} else {
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if (soft) {
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if (is_sfu(assigner)) {
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delay = 4;
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} else {
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delay = ir3_delayslots(assigner, consumer, srcn);
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}
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} else {
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delay = ir3_delayslots(assigner, consumer, srcn);
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}
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delay -= ir3_distance(block, assigner, delay, pred);
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}
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return delay;
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}
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static struct ir3_instruction *
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find_array_write(struct ir3_block *block, unsigned array_id, unsigned maxd)
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{
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unsigned d = 0;
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/* Note that this relies on incrementally building up the block's
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* instruction list.. but this is how scheduling and nopsched
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* work.
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*/
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foreach_instr_rev (n, &block->instr_list) {
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if (d >= maxd)
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return NULL;
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if (count_instruction(n))
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d++;
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if (dest_regs(n) == 0)
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continue;
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/* note that a dest reg will never be an immediate */
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if (n->regs[0]->array.id == array_id)
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return n;
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}
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return NULL;
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}
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/* like list_length() but only counts instructions which count in the
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* delay determination:
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*/
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static unsigned
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count_block_delay(struct ir3_block *block)
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{
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unsigned delay = 0;
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foreach_instr (n, &block->instr_list) {
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if (!count_instruction(n))
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continue;
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delay++;
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}
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return delay;
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}
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static unsigned
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delay_calc_array(struct ir3_block *block, unsigned array_id,
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struct ir3_instruction *consumer, unsigned srcn,
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bool soft, bool pred, unsigned maxd)
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{
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struct ir3_instruction *assigner;
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assigner = find_array_write(block, array_id, maxd);
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if (assigner)
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return delay_calc_srcn(block, assigner, consumer, srcn, soft, pred);
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if (!pred)
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return 0;
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unsigned len = count_block_delay(block);
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if (maxd <= len)
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return 0;
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maxd -= len;
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if (block->data == block) {
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/* we have a loop, return worst case: */
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return maxd;
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}
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/* If we need to search into predecessors, find the one with the
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* max delay.. the resulting delay is that minus the number of
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* counted instructions in this block:
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*/
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unsigned max = 0;
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/* (ab)use block->data to prevent recursion: */
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block->data = block;
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set_foreach (block->predecessors, entry) {
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struct ir3_block *pred = (struct ir3_block *)entry->key;
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unsigned delay =
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delay_calc_array(pred, array_id, consumer, srcn, soft, pred, maxd);
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max = MAX2(max, delay);
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}
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block->data = NULL;
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if (max < len)
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return 0;
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return max - len;
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}
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/**
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* Calculate delay for instruction (maximum of delay for all srcs):
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*
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* @soft: If true, add additional delay for situations where they
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* would not be strictly required because a sync flag would be
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* used (but scheduler would prefer to schedule some other
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* instructions first to avoid stalling on sync flag)
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* @pred: If true, recurse into predecessor blocks
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*/
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unsigned
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ir3_delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
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bool soft, bool pred)
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{
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unsigned delay = 0;
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struct ir3_register *src;
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foreach_src_n (src, i, instr) {
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unsigned d = 0;
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if ((src->flags & IR3_REG_RELATIV) && !(src->flags & IR3_REG_CONST)) {
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d = delay_calc_array(block, src->array.id, instr, i+1, soft, pred, 6);
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} else if (src->instr) {
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d = delay_calc_srcn(block, src->instr, instr, i+1, soft, pred);
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}
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delay = MAX2(delay, d);
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}
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if (instr->address) {
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unsigned d = delay_calc_srcn(block, instr->address, instr, 0, soft, pred);
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delay = MAX2(delay, d);
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}
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return delay;
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}
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@ -48,72 +48,6 @@
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* blocks depth sorted list, which is used by the scheduling pass.
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*/
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/* generally don't count false dependencies, since this can just be
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* something like a barrier, or SSBO store. The exception is array
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* dependencies if the assigner is an array write and the consumer
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* reads the same array.
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*/
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static bool
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ignore_dep(struct ir3_instruction *assigner,
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struct ir3_instruction *consumer, unsigned n)
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{
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if (!__is_false_dep(consumer, n))
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return false;
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if (assigner->barrier_class & IR3_BARRIER_ARRAY_W) {
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struct ir3_register *dst = assigner->regs[0];
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struct ir3_register *src;
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debug_assert(dst->flags & IR3_REG_ARRAY);
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foreach_src(src, consumer) {
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if ((src->flags & IR3_REG_ARRAY) &&
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(dst->array.id == src->array.id)) {
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return false;
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}
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}
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}
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return true;
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}
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/* calculate required # of delay slots between the instruction that
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* assigns a value and the one that consumes
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*/
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int ir3_delayslots(struct ir3_instruction *assigner,
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struct ir3_instruction *consumer, unsigned n)
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{
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if (ignore_dep(assigner, consumer, n))
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return 0;
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/* worst case is cat1-3 (alu) -> cat4/5 needing 6 cycles, normal
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* alu -> alu needs 3 cycles, cat4 -> alu and texture fetch
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* handled with sync bits
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*/
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if (is_meta(assigner) || is_meta(consumer))
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return 0;
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if (writes_addr(assigner))
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return 6;
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/* handled via sync flags: */
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if (is_sfu(assigner) || is_tex(assigner) || is_mem(assigner))
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return 0;
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/* assigner must be alu: */
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if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer) ||
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is_mem(consumer)) {
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return 6;
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} else if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
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(n == 3)) {
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/* special case, 3rd src to cat3 not required on first cycle */
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return 1;
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} else {
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return 3;
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}
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}
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void
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ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list)
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{
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@ -265,117 +265,6 @@ deepest(struct ir3_instruction **srcs, unsigned nsrcs)
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return d;
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}
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/**
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* @block: the block to search in, starting from end; in first pass,
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* this will be the block the instruction would be inserted into
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* (but has not yet, ie. it only contains already scheduled
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* instructions). For intra-block scheduling (second pass), this
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* would be one of the predecessor blocks.
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* @instr: the instruction to search for
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* @maxd: max distance, bail after searching this # of instruction
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* slots, since it means the instruction we are looking for is
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* far enough away
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* @pred: if true, recursively search into predecessor blocks to
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* find the worst case (shortest) distance (only possible after
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* individual blocks are all scheduled
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*/
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static unsigned
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distance(struct ir3_block *block, struct ir3_instruction *instr,
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unsigned maxd, bool pred)
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{
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unsigned d = 0;
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foreach_instr_rev (n, &block->instr_list) {
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if ((n == instr) || (d >= maxd))
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return d;
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/* NOTE: don't count branch/jump since we don't know yet if they will
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* be eliminated later in resolve_jumps().. really should do that
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* earlier so we don't have this constraint.
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*/
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if (is_alu(n) || (is_flow(n) && (n->opc != OPC_JUMP) && (n->opc != OPC_BR)))
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d++;
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}
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/* if coming from a predecessor block, assume it is assigned far
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* enough away.. we'll fix up later.
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*/
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if (!pred)
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return maxd;
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if (pred && (block->data != block)) {
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/* Search into predecessor blocks, finding the one with the
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* shortest distance, since that will be the worst case
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*/
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unsigned min = maxd - d;
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/* (ab)use block->data to prevent recursion: */
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block->data = block;
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set_foreach(block->predecessors, entry) {
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struct ir3_block *pred = (struct ir3_block *)entry->key;
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unsigned n;
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n = distance(pred, instr, min, pred);
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min = MIN2(min, n);
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}
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block->data = NULL;
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d += min;
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}
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return d;
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}
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/* calculate delay for specified src: */
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static unsigned
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delay_calc_srcn(struct ir3_block *block,
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struct ir3_instruction *assigner,
|
||||
struct ir3_instruction *consumer,
|
||||
unsigned srcn, bool soft, bool pred)
|
||||
{
|
||||
unsigned delay = 0;
|
||||
|
||||
if (is_meta(assigner)) {
|
||||
struct ir3_instruction *src;
|
||||
foreach_ssa_src(src, assigner) {
|
||||
unsigned d;
|
||||
d = delay_calc_srcn(block, src, consumer, srcn, soft, pred);
|
||||
delay = MAX2(delay, d);
|
||||
}
|
||||
} else {
|
||||
if (soft) {
|
||||
if (is_sfu(assigner)) {
|
||||
delay = 4;
|
||||
} else {
|
||||
delay = ir3_delayslots(assigner, consumer, srcn);
|
||||
}
|
||||
} else {
|
||||
delay = ir3_delayslots(assigner, consumer, srcn);
|
||||
}
|
||||
delay -= distance(block, assigner, delay, pred);
|
||||
}
|
||||
|
||||
return delay;
|
||||
}
|
||||
|
||||
/* calculate delay for instruction (maximum of delay for all srcs): */
|
||||
static unsigned
|
||||
delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
|
||||
bool soft, bool pred)
|
||||
{
|
||||
unsigned delay = 0;
|
||||
struct ir3_instruction *src;
|
||||
|
||||
foreach_ssa_src_n(src, i, instr) {
|
||||
unsigned d;
|
||||
d = delay_calc_srcn(block, src, instr, i, soft, pred);
|
||||
delay = MAX2(delay, d);
|
||||
}
|
||||
|
||||
return delay;
|
||||
}
|
||||
|
||||
struct ir3_sched_notes {
|
||||
/* there is at least one kill which could be scheduled, except
|
||||
* for unscheduled bary.f's:
|
||||
|
@ -658,7 +547,7 @@ find_eligible_instr(struct ir3_sched_ctx *ctx, struct ir3_sched_notes *notes,
|
|||
continue;
|
||||
}
|
||||
|
||||
int rank = delay_calc(ctx->block, candidate, soft, false);
|
||||
int rank = ir3_delay_calc(ctx->block, candidate, soft, false);
|
||||
|
||||
/* if too many live values, prioritize instructions that reduce the
|
||||
* number of live values:
|
||||
|
@ -827,7 +716,7 @@ sched_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
|||
instr = find_eligible_instr(ctx, ¬es, false);
|
||||
|
||||
if (instr) {
|
||||
unsigned delay = delay_calc(ctx->block, instr, false, false);
|
||||
unsigned delay = ir3_delay_calc(ctx->block, instr, false, false);
|
||||
|
||||
d("delay=%u", delay);
|
||||
|
||||
|
@ -886,7 +775,7 @@ sched_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
|||
debug_assert(ctx->pred);
|
||||
debug_assert(block->condition);
|
||||
|
||||
delay -= distance(ctx->block, ctx->pred, delay, false);
|
||||
delay -= ir3_distance(ctx->block, ctx->pred, delay, false);
|
||||
|
||||
while (delay > 0) {
|
||||
ir3_NOP(block);
|
||||
|
@ -944,7 +833,7 @@ sched_intra_block(struct ir3_sched_ctx *ctx, struct ir3_block *block)
|
|||
|
||||
set_foreach(block->predecessors, entry) {
|
||||
struct ir3_block *pred = (struct ir3_block *)entry->key;
|
||||
unsigned d = delay_calc(pred, instr, false, true);
|
||||
unsigned d = ir3_delay_calc(pred, instr, false, true);
|
||||
delay = MAX2(d, delay);
|
||||
}
|
||||
|
||||
|
|
|
@ -54,6 +54,7 @@ libfreedreno_ir3_files = files(
|
|||
'ir3_context.c',
|
||||
'ir3_context.h',
|
||||
'ir3_cp.c',
|
||||
'ir3_delay.c',
|
||||
'ir3_depth.c',
|
||||
'ir3_group.c',
|
||||
'ir3_image.c',
|
||||
|
|
Loading…
Reference in New Issue