radv: Use ac_surface to allocate aux surfaces.
For consistency and a bunch of codesharing. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5194>
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@ -1230,50 +1230,17 @@ radv_image_override_offset_stride(struct radv_device *device,
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}
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static void
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static void
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radv_image_alloc_fmask(struct radv_device *device,
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radv_image_alloc_single_sample_cmask(const struct radv_image *image,
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struct radv_image *image)
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struct radeon_surf *surf)
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{
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{
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unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
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if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 ||
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image->info.levels > 1 || image->info.depth > 1 ||
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image->planes[0].surface.fmask_offset = align64(image->size, fmask_alignment);
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!radv_image_use_fast_clear_for_image(image))
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image->size = image->planes[0].surface.fmask_offset + image->planes[0].surface.fmask_size;
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image->alignment = MAX2(image->alignment, fmask_alignment);
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}
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static void
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radv_image_alloc_cmask(struct radv_device *device,
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struct radv_image *image)
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{
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unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
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unsigned cmask_size = image->planes[0].surface.cmask_size;
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if (!cmask_size)
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return;
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return;
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assert(cmask_alignment);
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surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment);
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surf->total_size = surf->cmask_offset + surf->cmask_size;
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image->planes[0].surface.cmask_offset = align64(image->size, cmask_alignment);
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surf->alignment = MAX2(surf->alignment, surf->cmask_alignment);
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image->size = image->planes[0].surface.cmask_offset + cmask_size;
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image->alignment = MAX2(image->alignment, cmask_alignment);
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}
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static void
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radv_image_alloc_dcc(struct radv_image *image)
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{
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assert(image->plane_count == 1);
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image->planes[0].surface.dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
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image->size = image->planes[0].surface.dcc_offset + image->planes[0].surface.dcc_size;
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image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
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}
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static void
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radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
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{
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image->planes[0].surface.htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
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image->size = image->clear_value_offset;
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image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
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}
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}
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static void
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static void
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@ -1304,34 +1271,6 @@ radv_image_alloc_values(const struct radv_device *device, struct radv_image *ima
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}
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}
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}
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}
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static inline bool
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radv_image_can_enable_cmask(struct radv_image *image)
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{
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if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
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/* Do not enable CMASK for non-MSAA images (fast color clear)
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* because 128 bit formats are not supported, but FMASK might
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* still be used.
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*/
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return false;
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}
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return radv_image_use_fast_clear_for_image(image) &&
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image->info.levels == 1 &&
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image->info.depth == 1;
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}
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static void radv_image_disable_dcc(struct radv_image *image)
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{
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for (unsigned i = 0; i < image->plane_count; ++i)
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image->planes[i].surface.dcc_size = 0;
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}
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static void radv_image_disable_htile(struct radv_image *image)
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{
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for (unsigned i = 0; i < image->plane_count; ++i)
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image->planes[i].surface.htile_size = 0;
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}
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VkResult
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VkResult
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radv_image_create_layout(struct radv_device *device,
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radv_image_create_layout(struct radv_device *device,
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struct radv_image_create_info create_info,
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struct radv_image_create_info create_info,
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@ -1371,46 +1310,21 @@ radv_image_create_layout(struct radv_device *device,
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device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
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device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
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image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
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if (!create_info.no_metadata_planes && image->plane_count == 1)
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image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
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radv_image_alloc_single_sample_cmask(image, &image->planes[plane].surface);
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image->alignment = image->planes[plane].surface.surf_alignment;
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image->planes[plane].offset = align(image->size, image->planes[plane].surface.alignment);
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image->size = image->planes[plane].offset + image->planes[plane].surface.total_size;
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image->alignment = MAX2(image->alignment, image->planes[plane].surface.alignment);
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image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
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image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
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}
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}
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/* Try to enable DCC first. */
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image->tc_compatible_cmask = radv_image_has_cmask(image) &&
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if (radv_image_has_dcc(image)) {
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radv_use_tc_compat_cmask_for_image(device, image);
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radv_image_alloc_dcc(image);
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if (image->info.samples > 1) {
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/* CMASK should be enabled because DCC fast
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* clear with MSAA needs it.
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*/
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assert(radv_image_can_enable_cmask(image));
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radv_image_alloc_cmask(device, image);
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}
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} else {
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/* When DCC cannot be enabled, try CMASK. */
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radv_image_disable_dcc(image);
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if (radv_image_can_enable_cmask(image)) {
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radv_image_alloc_cmask(device, image);
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}
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}
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/* Try to enable FMASK for multisampled images. */
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image->tc_compatible_htile = radv_image_has_htile(image) &&
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if (image->planes[0].surface.fmask_size) {
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image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
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radv_image_alloc_fmask(device, image);
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if (radv_use_tc_compat_cmask_for_image(device, image))
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image->tc_compatible_cmask = true;
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} else {
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/* Otherwise, try to enable HTILE for depth surfaces. */
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if (radv_image_has_htile(image)) {
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image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
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radv_image_alloc_htile(device, image);
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} else {
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radv_image_disable_htile(image);
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}
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}
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radv_image_alloc_values(device, image);
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radv_image_alloc_values(device, image);
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