radeonsi: emit_spi_map packets optimization
v2: marek: remove an empty line before break; rename reg_val_seq -> spi_ps_input_cntl "type * x" -> "type *x" Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
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4d094993c3
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c6737756ad
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@ -214,4 +214,26 @@ static inline void radeon_opt_set_context_reg4(struct si_context *sctx, unsigned
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}
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}
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/**
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* Set consecutive registers if any registers value is different.
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*/
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static inline void radeon_opt_set_context_regn(struct si_context *sctx, unsigned offset,
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unsigned *value, unsigned *saved_val,
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unsigned num)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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int i, j;
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for (i = 0; i < num; i++) {
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if (saved_val[i] != value[i]) {
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radeon_set_context_reg_seq(cs, offset, num);
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for (j = 0; j < num; j++)
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radeon_emit(cs, value[j]);
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memcpy(saved_val, value, sizeof(uint32_t) * num);
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break;
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}
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}
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}
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#endif
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@ -353,4 +353,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
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/* Set all saved registers state to unknown. */
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ctx->tracked_regs.reg_saved = 0;
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}
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/* 0xffffffff is a impossible value to register SPI_PS_INPUT_CNTL_n */
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memset(ctx->tracked_regs.spi_ps_input_cntl, 0xff, sizeof(uint32_t) * 32);
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}
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@ -287,6 +287,7 @@ enum si_tracked_reg {
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struct si_tracked_regs {
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uint32_t reg_saved;
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uint32_t reg_value[SI_NUM_TRACKED_REGS];
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uint32_t spi_ps_input_cntl[32];
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};
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/* Private read-write buffer slots. */
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@ -2634,27 +2634,25 @@ static unsigned si_get_ps_input_cntl(struct si_context *sctx,
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static void si_emit_spi_map(struct si_context *sctx)
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{
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struct radeon_cmdbuf *cs = sctx->gfx_cs;
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struct si_shader *ps = sctx->ps_shader.current;
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struct si_shader *vs = si_get_vs_state(sctx);
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struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
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unsigned i, num_interp, num_written = 0, bcol_interp[2];
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unsigned spi_ps_input_cntl[32];
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if (!ps || !ps->selector->info.num_inputs)
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return;
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num_interp = si_get_ps_num_interp(ps);
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assert(num_interp > 0);
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radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
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for (i = 0; i < psinfo->num_inputs; i++) {
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unsigned name = psinfo->input_semantic_name[i];
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unsigned index = psinfo->input_semantic_index[i];
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unsigned interpolate = psinfo->input_interpolate[i];
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radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
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interpolate));
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num_written++;
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spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
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index, interpolate);
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if (name == TGSI_SEMANTIC_COLOR) {
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assert(index < ARRAY_SIZE(bcol_interp));
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@ -2669,12 +2667,19 @@ static void si_emit_spi_map(struct si_context *sctx)
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if (!(psinfo->colors_read & (0xf << (i * 4))))
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continue;
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radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
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i, bcol_interp[i]));
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num_written++;
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spi_ps_input_cntl[num_written++] =
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si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
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}
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}
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assert(num_interp == num_written);
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/* R_028644_SPI_PS_INPUT_CNTL_0 */
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/* Dota 2: Only ~16% of SPI map updates set different values. */
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/* Talos: Only ~9% of SPI map updates set different values. */
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radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
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spi_ps_input_cntl,
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sctx->tracked_regs.spi_ps_input_cntl, num_interp);
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}
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/**
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