intel/fs: Choose memory message type based on bit size
Thanks to the NIR vectorizing pass, we're about to see alignments that are higher than the bit size. Previously, we could use either and we just happened to choose alignment (probably the wrong choice) so it's harmless to switch to detecting based on bit size. This commit changes things to take both into account which is more accurate to what the messages we're using do. We also beef up the asserts and make them more consistent, more accurate, and more complete. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4367>
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@ -3890,15 +3890,17 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
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dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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/* Read the vector */
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_bit_size(instr->dest) == 32);
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_intrinsic_align(instr) > 0);
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if (nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_num_components(instr->dest) <= 4);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
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fs_inst *inst =
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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inst->size_written = instr->num_components * dispatch_width * 4;
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} else {
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_dest_num_components(instr->dest) == 1);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
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@ -3923,17 +3925,18 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
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fs_reg data = get_nir_src(instr->src[0]);
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data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_intrinsic_write_mask(instr) ==
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(1u << instr->num_components) - 1);
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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assert(nir_intrinsic_align(instr) > 0);
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if (nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_num_components(instr->src[0]) <= 4);
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_src_num_components(instr->src[0]) == 1);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
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@ -4556,8 +4559,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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case nir_intrinsic_load_global: {
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assert(devinfo->gen >= 8);
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_bit_size(instr->dest) == 32);
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_intrinsic_align(instr) > 0);
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if (nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_num_components(instr->dest) <= 4);
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fs_inst *inst = bld.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
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dest,
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get_nir_src(instr->src[0]), /* Address */
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@ -4567,7 +4573,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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inst->dst.component_size(inst->exec_size);
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} else {
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const unsigned bit_size = nir_dest_bit_size(instr->dest);
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assert(bit_size <= 32);
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assert(nir_dest_num_components(instr->dest) == 1);
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fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
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@ -4586,17 +4591,21 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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if (stage == MESA_SHADER_FRAGMENT)
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brw_wm_prog_data(prog_data)->has_side_effects = true;
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_intrinsic_write_mask(instr) ==
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(1u << instr->num_components) - 1);
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assert(nir_intrinsic_align(instr) > 0);
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if (nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_num_components(instr->src[0]) <= 4);
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bld.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
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fs_reg(),
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get_nir_src(instr->src[1]), /* Address */
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get_nir_src(instr->src[0]), /* Data */
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brw_imm_ud(instr->num_components));
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} else {
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const unsigned bit_size = nir_src_bit_size(instr->src[0]);
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assert(bit_size <= 32);
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assert(nir_src_num_components(instr->src[0]) == 1);
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const unsigned bit_size = nir_src_bit_size(instr->src[0]);
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brw_reg_type data_type =
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brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD);
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@ -4641,15 +4650,17 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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/* Read the vector */
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_bit_size(instr->dest) == 32);
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_intrinsic_align(instr) > 0);
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if (nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_num_components(instr->dest) <= 4);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
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fs_inst *inst =
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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inst->size_written = instr->num_components * dispatch_width * 4;
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} else {
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_dest_num_components(instr->dest) == 1);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
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@ -4677,17 +4688,18 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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fs_reg data = get_nir_src(instr->src[0]);
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data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_intrinsic_write_mask(instr) ==
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(1u << instr->num_components) - 1);
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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assert(nir_intrinsic_align(instr) > 0);
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if (nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_num_components(instr->src[0]) <= 4);
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_src_num_components(instr->src[0]) == 1);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
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@ -4816,9 +4828,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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/* Read the vector */
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_dest_bit_size(instr->dest) == 32);
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assert(nir_dest_num_components(instr->dest) == 1);
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_intrinsic_align(instr) > 1);
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if (nir_dest_bit_size(instr->dest) >= 4 &&
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nir_intrinsic_align(instr) >= 4) {
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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@ -4826,8 +4840,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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assert(nir_dest_bit_size(instr->dest) <= 32);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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@ -4860,10 +4872,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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fs_reg data = get_nir_src(instr->src[0]);
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data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
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assert(nir_intrinsic_write_mask(instr) ==
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(1u << instr->num_components) - 1);
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if (nir_intrinsic_align(instr) >= 4) {
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assert(nir_src_bit_size(instr->src[0]) == 32);
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assert(nir_src_num_components(instr->src[0]) == 1);
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_intrinsic_write_mask(instr) == 1);
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assert(nir_intrinsic_align(instr) > 1);
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if (nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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/* The offset for a DWORD scattered message is in dwords. */
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@ -4873,8 +4887,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
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