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freedreno: shader_t -> gl_shader_stage 

Just massive search/replace for the most part.

Step towards removing ir3 dependency on disasm.h which is shared by
a2xx.  One step closer to being able to move ir3 out of gallium.

Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2018-11-09 10:47:14 -05:00
parent 388aac32ed
commit c635703c50
22 changed files with 121 additions and 143 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/gallium/drivers/freedreno/a2xx/disasm-a2xx.c
View File

@ -96,17 +96,17 @@ static void print_dstreg(uint32_t num, uint32_t mask, uint32_t dst_exp)
}
}
static void print_export_comment(uint32_t num, enum shader_t type)
static void print_export_comment(uint32_t num, gl_shader_stage type)
{
const char *name = NULL;
switch (type) {
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
switch (num) {
case 62: name = "gl_Position"; break;
case 63: name = "gl_PointSize"; break;
}
break;
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
switch (num) {
case 0: name = "gl_FragColor"; break;
}
@ -212,7 +212,7 @@ struct {
};
static int disasm_alu(uint32_t *dwords, uint32_t alu_off,
int level, int sync, enum shader_t type)
int level, int sync, gl_shader_stage type)
{
instr_alu_t *alu = (instr_alu_t *)dwords;
@ -592,7 +592,7 @@ static void print_cf(instr_cf_t *cf, int level)
* 2) ALU and FETCH instructions
*/
int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, enum shader_t type)
int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type)
{
instr_cf_t *cfs = (instr_cf_t *)dwords;
int idx, max_idx;

16
src/gallium/drivers/freedreno/a2xx/fd2_program.c
View File

@ -40,7 +40,7 @@
#include "fd2_util.h"
static struct fd2_shader_stateobj *
create_shader(enum shader_t type)
create_shader(gl_shader_stage type)
{
struct fd2_shader_stateobj *so = CALLOC_STRUCT(fd2_shader_stateobj);
if (!so)
@ -119,7 +119,7 @@ emit(struct fd_ringbuffer *ring, struct fd2_shader_stateobj *so)
assemble(so);
OUT_PKT3(ring, CP_IM_LOAD_IMMEDIATE, 2 + so->info.sizedwords);
OUT_RING(ring, (so->type == SHADER_VERTEX) ? 0 : 1);
OUT_RING(ring, (so->type == MESA_SHADER_VERTEX) ? 0 : 1);
OUT_RING(ring, so->info.sizedwords);
for (i = 0; i < so->info.sizedwords; i++)
OUT_RING(ring, so->bin[i]);
@ -129,7 +129,7 @@ static void *
fd2_fp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
struct fd2_shader_stateobj *so = create_shader(SHADER_FRAGMENT);
struct fd2_shader_stateobj *so = create_shader(MESA_SHADER_FRAGMENT);
if (!so)
return NULL;
so->tokens = tgsi_dup_tokens(cso->tokens);
@ -147,7 +147,7 @@ static void *
fd2_vp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
struct fd2_shader_stateobj *so = create_shader(SHADER_VERTEX);
struct fd2_shader_stateobj *so = create_shader(MESA_SHADER_VERTEX);
if (!so)
return NULL;
so->tokens = tgsi_dup_tokens(cso->tokens);
@ -304,7 +304,7 @@ fd2_program_emit(struct fd_ringbuffer *ring,
static struct fd2_shader_stateobj *
create_blit_fp(void)
{
struct fd2_shader_stateobj *so = create_shader(SHADER_FRAGMENT);
struct fd2_shader_stateobj *so = create_shader(MESA_SHADER_FRAGMENT);
struct ir2_instruction *instr;
if (!so)
@ -340,7 +340,7 @@ create_blit_fp(void)
static struct fd2_shader_stateobj *
create_blit_vp(void)
{
struct fd2_shader_stateobj *so = create_shader(SHADER_VERTEX);
struct fd2_shader_stateobj *so = create_shader(MESA_SHADER_VERTEX);
struct ir2_instruction *instr;
if (!so)
@ -379,7 +379,7 @@ create_blit_vp(void)
static struct fd2_shader_stateobj *
create_solid_fp(void)
{
struct fd2_shader_stateobj *so = create_shader(SHADER_FRAGMENT);
struct fd2_shader_stateobj *so = create_shader(MESA_SHADER_FRAGMENT);
struct ir2_instruction *instr;
if (!so)
@ -408,7 +408,7 @@ create_solid_fp(void)
static struct fd2_shader_stateobj *
create_solid_vp(void)
{
struct fd2_shader_stateobj *so = create_shader(SHADER_VERTEX);
struct fd2_shader_stateobj *so = create_shader(MESA_SHADER_VERTEX);
struct ir2_instruction *instr;
if (!so)

2
src/gallium/drivers/freedreno/a2xx/fd2_program.h
View File

@ -35,7 +35,7 @@
#include "disasm.h"
struct fd2_shader_stateobj {
enum shader_t type;
gl_shader_stage type;
uint32_t *bin;

8
src/gallium/drivers/freedreno/a3xx/fd3_emit.c
View File

@ -44,8 +44,8 @@
#include "fd3_zsa.h"
static const enum adreno_state_block sb[] = {
[SHADER_VERTEX] = SB_VERT_SHADER,
[SHADER_FRAGMENT] = SB_FRAG_SHADER,
[MESA_SHADER_VERTEX] = SB_VERT_SHADER,
[MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
};
/* regid: base const register
@ -53,7 +53,7 @@ static const enum adreno_state_block sb[] = {
* sizedwords: size of const value buffer
*/
static void
fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
fd3_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
{
@ -91,7 +91,7 @@ fd3_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
}
static void
fd3_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
fd3_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
uint32_t anum = align(num, 4);

8
src/gallium/drivers/freedreno/a3xx/fd3_program.c
View File

@ -40,7 +40,7 @@
static struct ir3_shader *
create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
enum shader_t type)
gl_shader_stage type)
{
struct fd_context *ctx = fd_context(pctx);
struct ir3_compiler *compiler = ctx->screen->compiler;
@ -51,7 +51,7 @@ static void *
fd3_fp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
}
static void
@ -65,7 +65,7 @@ static void *
fd3_vp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
}
static void
@ -97,7 +97,7 @@ emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
enum adreno_state_src src;
uint32_t i, sz, *bin;
if (so->type == SHADER_VERTEX) {
if (so->type == MESA_SHADER_VERTEX) {
sb = SB_VERT_SHADER;
} else {
sb = SB_FRAG_SHADER;

4
src/gallium/drivers/freedreno/a4xx/fd4_emit.c
View File

@ -48,7 +48,7 @@
* sizedwords: size of const value buffer
*/
static void
fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
fd4_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
{
@ -86,7 +86,7 @@ fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
}
static void
fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
uint32_t anum = align(num, 4);

6
src/gallium/drivers/freedreno/a4xx/fd4_program.c
View File

@ -39,7 +39,7 @@
static struct ir3_shader *
create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
enum shader_t type)
gl_shader_stage type)
{
struct fd_context *ctx = fd_context(pctx);
struct ir3_compiler *compiler = ctx->screen->compiler;
@ -50,7 +50,7 @@ static void *
fd4_fp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
}
static void
@ -64,7 +64,7 @@ static void *
fd4_vp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
}
static void

4
src/gallium/drivers/freedreno/a5xx/fd5_emit.c
View File

@ -51,7 +51,7 @@
* sizedwords: size of const value buffer
*/
static void
fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
fd5_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
{
@ -90,7 +90,7 @@ fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
}
static void
fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
fd5_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
uint32_t anum = align(num, 2);

6
src/gallium/drivers/freedreno/a5xx/fd5_program.c
View File

@ -42,7 +42,7 @@
static struct ir3_shader *
create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
enum shader_t type)
gl_shader_stage type)
{
struct fd_context *ctx = fd_context(pctx);
struct ir3_compiler *compiler = ctx->screen->compiler;
@ -53,7 +53,7 @@ static void *
fd5_fp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
}
static void
@ -67,7 +67,7 @@ static void *
fd5_vp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
}
static void

18
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View File

@ -46,16 +46,16 @@
#include "fd6_zsa.h"
static uint32_t
shader_t_to_opcode(enum shader_t type)
shader_t_to_opcode(gl_shader_stage type)
{
switch (type) {
case SHADER_VERTEX:
case SHADER_TCS:
case SHADER_TES:
case SHADER_GEOM:
case MESA_SHADER_VERTEX:
case MESA_SHADER_TESS_CTRL:
case MESA_SHADER_TESS_EVAL:
case MESA_SHADER_GEOMETRY:
return CP_LOAD_STATE6_GEOM;
case SHADER_FRAGMENT:
case SHADER_COMPUTE:
case MESA_SHADER_FRAGMENT:
case MESA_SHADER_COMPUTE:
return CP_LOAD_STATE6_FRAG;
default:
unreachable("bad shader type");
@ -67,7 +67,7 @@ shader_t_to_opcode(enum shader_t type)
* sizedwords: size of const value buffer
*/
static void
fd6_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc)
{
@ -105,7 +105,7 @@ fd6_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
}
static void
fd6_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
{
uint32_t anum = align(num, 2);

8
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
View File

@ -155,14 +155,14 @@ fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
}
static inline enum a6xx_state_block
fd6_stage2shadersb(enum shader_t type)
fd6_stage2shadersb(gl_shader_stage type)
{
switch (type) {
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return SB6_VS_SHADER;
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
return SB6_FS_SHADER;
case SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
return SB6_CS_SHADER;
default:
unreachable("bad shader type");

12
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View File

@ -41,7 +41,7 @@
static struct ir3_shader *
create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
enum shader_t type)
gl_shader_stage type)
{
struct fd_context *ctx = fd_context(pctx);
struct ir3_compiler *compiler = ctx->screen->compiler;
@ -52,7 +52,7 @@ static void *
fd6_fp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
}
static void
@ -68,7 +68,7 @@ static void *
fd6_vp_state_create(struct pipe_context *pctx,
const struct pipe_shader_state *cso)
{
return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
}
static void
@ -100,11 +100,11 @@ fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
}
switch (so->type) {
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
opcode = CP_LOAD_STATE6_GEOM;
break;
case SHADER_FRAGMENT:
case SHADER_COMPUTE:
case MESA_SHADER_FRAGMENT:
case MESA_SHADER_COMPUTE:
opcode = CP_LOAD_STATE6_FRAG;
break;
default:

35
src/gallium/drivers/freedreno/disasm.h
View File

@ -27,6 +27,7 @@
#include <stdio.h>
#include <stdbool.h>
#include "compiler/shader_enums.h"
#include "util/u_debug.h"
enum fd_shader_debug {
@ -37,23 +38,13 @@ enum fd_shader_debug {
extern enum fd_shader_debug fd_shader_debug;
enum shader_t {
SHADER_VERTEX,
SHADER_TCS,
SHADER_TES,
SHADER_GEOM,
SHADER_FRAGMENT,
SHADER_COMPUTE,
SHADER_MAX,
};
static inline bool
shader_debug_enabled(enum shader_t type)
shader_debug_enabled(gl_shader_stage type)
{
switch (type) {
case SHADER_VERTEX: return !!(fd_shader_debug & FD_DBG_SHADER_VS);
case SHADER_FRAGMENT: return !!(fd_shader_debug & FD_DBG_SHADER_FS);
case SHADER_COMPUTE: return !!(fd_shader_debug & FD_DBG_SHADER_CS);
case MESA_SHADER_VERTEX: return !!(fd_shader_debug & FD_DBG_SHADER_VS);
case MESA_SHADER_FRAGMENT: return !!(fd_shader_debug & FD_DBG_SHADER_FS);
case MESA_SHADER_COMPUTE: return !!(fd_shader_debug & FD_DBG_SHADER_CS);
default:
debug_assert(0);
return false;
@ -61,18 +52,18 @@ shader_debug_enabled(enum shader_t type)
}
static inline const char *
shader_stage_name(enum shader_t type)
shader_stage_name(gl_shader_stage type)
{
/* NOTE these names are chosen to match the INTEL_DEBUG output
* which frameretrace parses. Hurray accidental ABI!
*/
switch (type) {
case SHADER_VERTEX: return "vertex";
case SHADER_TCS: return "tessellation control";
case SHADER_TES: return "tessellation evaluation";
case SHADER_GEOM: return "geometry";
case SHADER_FRAGMENT: return "fragment";
case SHADER_COMPUTE: return "compute";
case MESA_SHADER_VERTEX: return "vertex";
case MESA_SHADER_TESS_CTRL: return "tessellation control";
case MESA_SHADER_TESS_EVAL: return "tessellation evaluation";
case MESA_SHADER_GEOMETRY: return "geometry";
case MESA_SHADER_FRAGMENT: return "fragment";
case MESA_SHADER_COMPUTE: return "compute";
default:
debug_assert(0);
return NULL;
@ -85,7 +76,7 @@ enum debug_t {
PRINT_VERBOSE = 0x2,
};
int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, enum shader_t type);
int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type);
int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out);
void disasm_set_debug(enum debug_t debug);

4
src/gallium/drivers/freedreno/freedreno_context.h
View File

@ -324,11 +324,11 @@ struct fd_context {
void (*launch_grid)(struct fd_context *ctx, const struct pipe_grid_info *info);
/* constant emit: (note currently not used/needed for a2xx) */
void (*emit_const)(struct fd_ringbuffer *ring, enum shader_t type,
void (*emit_const)(struct fd_ringbuffer *ring, gl_shader_stage type,
uint32_t regid, uint32_t offset, uint32_t sizedwords,
const uint32_t *dwords, struct pipe_resource *prsc);
/* emit bo addresses as constant: */
void (*emit_const_bo)(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
void (*emit_const_bo)(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets);
/* indirect-branch emit: */

8
src/gallium/drivers/freedreno/freedreno_util.h
View File

@ -464,14 +464,14 @@ fd_msaa_samples(unsigned samples)
*/
static inline enum a4xx_state_block
fd4_stage2shadersb(enum shader_t type)
fd4_stage2shadersb(gl_shader_stage type)
{
switch (type) {
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
return SB4_VS_SHADER;
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
return SB4_FS_SHADER;
case SHADER_COMPUTE:
case MESA_SHADER_COMPUTE:
return SB4_CS_SHADER;
default:
unreachable("bad shader type");

4
src/gallium/drivers/freedreno/ir3/ir3.h
View File

@ -31,7 +31,7 @@
#include "util/list.h"
#include "instr-a3xx.h"
#include "disasm.h" /* TODO move 'enum shader_t' somewhere else.. */
#include "disasm.h" /* TODO move 'gl_shader_stage' somewhere else.. */
/* low level intermediate representation of an adreno shader program */
@ -1002,7 +1002,7 @@ int ir3_sched(struct ir3 *ir);
/* register assignment: */
struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
int ir3_ra(struct ir3 *ir3, enum shader_t type,
int ir3_ra(struct ir3 *ir3, gl_shader_stage type,
bool frag_coord, bool frag_face);
/* legalize: */

15
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
View File

@ -484,20 +484,7 @@ int main(int argc, char **argv)
v.key = key;
v.shader = &s;
switch (nir->info.stage) {
case MESA_SHADER_FRAGMENT:
s.type = v.type = SHADER_FRAGMENT;
break;
case MESA_SHADER_VERTEX:
s.type = v.type = SHADER_VERTEX;
break;
case MESA_SHADER_COMPUTE:
s.type = v.type = SHADER_COMPUTE;
break;
default:
errx(1, "unhandled shader stage: %d", nir->info.stage);
}
s.type = v.type = nir->info.stage;
info = "NIR compiler";
ret = ir3_compile_shader_nir(s.compiler, &v);

44
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
View File

@ -139,16 +139,16 @@ compile_init(struct ir3_compiler *compiler,
struct ir3_context *ctx = rzalloc(NULL, struct ir3_context);
if (compiler->gpu_id >= 400) {
if (so->type == SHADER_VERTEX) {
if (so->type == MESA_SHADER_VERTEX) {
ctx->astc_srgb = so->key.vastc_srgb;
} else if (so->type == SHADER_FRAGMENT) {
} else if (so->type == MESA_SHADER_FRAGMENT) {
ctx->astc_srgb = so->key.fastc_srgb;
}
} else {
if (so->type == SHADER_VERTEX) {
if (so->type == MESA_SHADER_VERTEX) {
ctx->samples = so->key.vsamples;
} else if (so->type == SHADER_FRAGMENT) {
} else if (so->type == MESA_SHADER_FRAGMENT) {
ctx->samples = so->key.fsamples;
}
}
@ -238,16 +238,16 @@ compile_init(struct ir3_compiler *compiler,
}
unsigned num_driver_params = 0;
if (so->type == SHADER_VERTEX) {
if (so->type == MESA_SHADER_VERTEX) {
num_driver_params = IR3_DP_VS_COUNT;
} else if (so->type == SHADER_COMPUTE) {
} else if (so->type == MESA_SHADER_COMPUTE) {
num_driver_params = IR3_DP_CS_COUNT;
}
so->constbase.driver_param = constoff;
constoff += align(num_driver_params, 4) / 4;
if ((so->type == SHADER_VERTEX) &&
if ((so->type == MESA_SHADER_VERTEX) &&
(compiler->gpu_id < 500) &&
so->shader->stream_output.num_outputs > 0) {
so->constbase.tfbo = constoff;
@ -3219,7 +3219,7 @@ emit_function(struct ir3_context *ctx, nir_function_impl *impl)
if ((ctx->compiler->gpu_id < 500) &&
(ctx->so->shader->stream_output.num_outputs > 0) &&
!ctx->so->binning_pass) {
debug_assert(ctx->so->type == SHADER_VERTEX);
debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
emit_stream_out(ctx);
}
@ -3295,7 +3295,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
so->inputs_count = MAX2(so->inputs_count, n + 1);
so->inputs[n].interpolate = in->data.interpolation;
if (ctx->so->type == SHADER_FRAGMENT) {
if (ctx->so->type == MESA_SHADER_FRAGMENT) {
for (int i = 0; i < ncomp; i++) {
struct ir3_instruction *instr = NULL;
unsigned idx = (n * 4) + i;
@ -3351,7 +3351,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
ctx->ir->inputs[idx] = instr;
}
} else if (ctx->so->type == SHADER_VERTEX) {
} else if (ctx->so->type == MESA_SHADER_VERTEX) {
for (int i = 0; i < ncomp; i++) {
unsigned idx = (n * 4) + i;
compile_assert(ctx, idx < ctx->ir->ninputs);
@ -3361,7 +3361,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
compile_error(ctx, "unknown shader type: %d\n", ctx->so->type);
}
if (so->inputs[n].bary || (ctx->so->type == SHADER_VERTEX)) {
if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
so->total_in += ncomp;
}
}
@ -3383,7 +3383,7 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
ncomp = MAX2(ncomp, 4);
compile_assert(ctx, ncomp == 4);
if (ctx->so->type == SHADER_FRAGMENT) {
if (ctx->so->type == MESA_SHADER_FRAGMENT) {
switch (slot) {
case FRAG_RESULT_DEPTH:
comp = 2; /* tgsi will write to .z component */
@ -3398,7 +3398,7 @@ setup_output(struct ir3_context *ctx, nir_variable *out)
compile_error(ctx, "unknown FS output name: %s\n",
gl_frag_result_name(slot));
}
} else if (ctx->so->type == SHADER_VERTEX) {
} else if (ctx->so->type == MESA_SHADER_VERTEX) {
switch (slot) {
case VARYING_SLOT_POS:
so->writes_pos = true;
@ -3450,10 +3450,10 @@ max_drvloc(struct exec_list *vars)
return drvloc;
}
static const unsigned max_sysvals[SHADER_MAX] = {
[SHADER_FRAGMENT] = 24, // TODO
[SHADER_VERTEX] = 16,
[SHADER_COMPUTE] = 16, // TODO how many do we actually need?
static const unsigned max_sysvals[] = {
[MESA_SHADER_FRAGMENT] = 24, // TODO
[MESA_SHADER_VERTEX] = 16,
[MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
};
static void
@ -3482,7 +3482,7 @@ emit_instructions(struct ir3_context *ctx)
* base for bary.f varying fetch instrs:
*/
struct ir3_instruction *vcoord = NULL;
if (ctx->so->type == SHADER_FRAGMENT) {
if (ctx->so->type == MESA_SHADER_FRAGMENT) {
struct ir3_instruction *xy[2];
vcoord = create_input_compmask(ctx, 0, 0x3);
@ -3643,7 +3643,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
inputs = ir->inputs;
/* but fixup actual inputs for frag shader: */
if (so->type == SHADER_FRAGMENT)
if (so->type == MESA_SHADER_FRAGMENT)
fixup_frag_inputs(ctx);
/* at this point, for binning pass, throw away unneeded outputs: */
@ -3774,7 +3774,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
reg = in->regs[0]->num - j;
actual_in++;
so->inputs[i].ncomp++;
if ((so->type == SHADER_FRAGMENT) && so->inputs[i].bary) {
if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
/* assign inloc: */
assert(in->regs[1]->flags & IR3_REG_IMMED);
in->regs[1]->iim_val = inloc + j;
@ -3782,7 +3782,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
}
}
}
if ((so->type == SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
so->varying_in++;
so->inputs[i].compmask = (1 << maxcomp) - 1;
inloc += maxcomp;
@ -3806,7 +3806,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
}
/* Note that actual_in counts inputs that are not bary.f'd for FS: */
if (so->type == SHADER_VERTEX)
if (so->type == MESA_SHADER_VERTEX)
so->total_in = actual_in;
else
so->total_in = max_bary + 1;

4
src/gallium/drivers/freedreno/ir3/ir3_nir.c
View File

@ -137,12 +137,12 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
if (key) {
switch (shader->type) {
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
tex_options.saturate_s = key->fsaturate_s;
tex_options.saturate_t = key->fsaturate_t;
tex_options.saturate_r = key->fsaturate_r;
break;
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
tex_options.saturate_s = key->vsaturate_s;
tex_options.saturate_t = key->vsaturate_t;
tex_options.saturate_r = key->vsaturate_r;

4
src/gallium/drivers/freedreno/ir3/ir3_ra.c
View File

@ -326,7 +326,7 @@ struct ir3_ra_instr_data {
/* register-assign context, per-shader */
struct ir3_ra_ctx {
struct ir3 *ir;
enum shader_t type;
gl_shader_stage type;
bool frag_face;
struct ir3_ra_reg_set *set;
@ -1106,7 +1106,7 @@ retry:
return 0;
}
int ir3_ra(struct ir3 *ir, enum shader_t type,
int ir3_ra(struct ir3 *ir, gl_shader_stage type,
bool frag_coord, bool frag_face)
{
struct ir3_ra_ctx ctx = {

32
src/gallium/drivers/freedreno/ir3/ir3_shader.c
View File

@ -153,7 +153,7 @@ assemble_variant(struct ir3_shader_variant *v)
if (shader_debug_enabled(v->shader->type)) {
fprintf(stderr, "Native code for unnamed %s shader %s:\n",
shader_stage_name(v->shader->type), v->shader->nir->info.name);
if (v->shader->type == SHADER_FRAGMENT)
if (v->shader->type == MESA_SHADER_FRAGMENT)
fprintf(stderr, "SIMD0\n");
ir3_shader_disasm(v, bin, stderr);
}
@ -239,7 +239,7 @@ shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
* variants:
*/
switch (shader->type) {
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
if (key.has_per_samp) {
key.vsaturate_s = 0;
key.vsaturate_t = 0;
@ -248,7 +248,7 @@ shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
key.vsamples = 0;
}
break;
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
key.color_two_side = false;
key.half_precision = false;
key.rasterflat = false;
@ -312,7 +312,7 @@ ir3_shader_destroy(struct ir3_shader *shader)
struct ir3_shader *
ir3_shader_create(struct ir3_compiler *compiler,
const struct pipe_shader_state *cso, enum shader_t type,
const struct pipe_shader_state *cso, gl_shader_stage type,
struct pipe_debug_callback *debug)
{
struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
@ -366,7 +366,7 @@ ir3_shader_create_compute(struct ir3_compiler *compiler,
shader->compiler = compiler;
shader->id = ++shader->compiler->shader_count;
shader->type = SHADER_COMPUTE;
shader->type = MESA_SHADER_COMPUTE;
nir_shader *nir;
if (cso->ir_type == PIPE_SHADER_IR_NIR) {
@ -456,7 +456,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
disasm_a3xx(bin, so->info.sizedwords, 0, out);
switch (so->type) {
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
fprintf(out, "; %s: outputs:", type);
for (i = 0; i < so->outputs_count; i++) {
uint8_t regid = so->outputs[i].regid;
@ -476,7 +476,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
}
fprintf(out, "\n");
break;
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
fprintf(out, "; %s: outputs:", type);
for (i = 0; i < so->outputs_count; i++) {
uint8_t regid = so->outputs[i].regid;
@ -517,11 +517,11 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
/* print shader type specific info: */
switch (so->type) {
case SHADER_VERTEX:
case MESA_SHADER_VERTEX:
dump_output(out, so, VARYING_SLOT_POS, "pos");
dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
break;
case SHADER_FRAGMENT:
case MESA_SHADER_FRAGMENT:
dump_reg(out, "pos (bary)",
ir3_find_sysval_regid(so, SYSTEM_VALUE_VARYING_COORD));
dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
@ -874,7 +874,7 @@ void
ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
struct fd_context *ctx, const struct pipe_draw_info *info)
{
debug_assert(v->type == SHADER_VERTEX);
debug_assert(v->type == MESA_SHADER_VERTEX);
emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
@ -939,12 +939,12 @@ ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
ctx->mem_to_mem(ring, vertex_params_rsc, 0,
indirect->buffer, src_off, 1);
ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
ctx->emit_const(ring, MESA_SHADER_VERTEX, offset * 4, 0,
vertex_params_size, NULL, vertex_params_rsc);
pipe_resource_reference(&vertex_params_rsc, NULL);
} else {
ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
ctx->emit_const(ring, MESA_SHADER_VERTEX, offset * 4, 0,
vertex_params_size, vertex_params, NULL);
}
@ -960,7 +960,7 @@ void
ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
struct fd_context *ctx)
{
debug_assert(v->type == SHADER_FRAGMENT);
debug_assert(v->type == MESA_SHADER_FRAGMENT);
emit_common_consts(v, ring, ctx, PIPE_SHADER_FRAGMENT);
}
@ -970,7 +970,7 @@ void
ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
struct fd_context *ctx, const struct pipe_grid_info *info)
{
debug_assert(v->type == SHADER_COMPUTE);
debug_assert(v->type == MESA_SHADER_COMPUTE);
emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
@ -1004,7 +1004,7 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
indirect_offset = info->indirect_offset;
}
ctx->emit_const(ring, SHADER_COMPUTE, offset * 4,
ctx->emit_const(ring, MESA_SHADER_COMPUTE, offset * 4,
indirect_offset, 4, NULL, indirect);
pipe_resource_reference(&indirect, NULL);
@ -1018,7 +1018,7 @@ ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *rin
[IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
};
ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
ctx->emit_const(ring, MESA_SHADER_COMPUTE, offset * 4, 0,
ARRAY_SIZE(compute_params), compute_params, NULL);
}
}

12
src/gallium/drivers/freedreno/ir3/ir3_shader.h
View File

@ -345,12 +345,12 @@ struct ir3_shader_variant {
struct ir3_shader_variant *next;
/* replicated here to avoid passing extra ptrs everywhere: */
enum shader_t type;
gl_shader_stage type;
struct ir3_shader *shader;
};
struct ir3_shader {
enum shader_t type;
gl_shader_stage type;
/* shader id (for debug): */
uint32_t id;
@ -370,7 +370,7 @@ struct ir3_shader {
void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
const struct pipe_shader_state *cso, enum shader_t type,
const struct pipe_shader_state *cso, gl_shader_stage type,
struct pipe_debug_callback *debug);
struct ir3_shader *
ir3_shader_create_compute(struct ir3_compiler *compiler,
@ -399,9 +399,9 @@ static inline const char *
ir3_shader_stage(struct ir3_shader *shader)
{
switch (shader->type) {
case SHADER_VERTEX: return "VERT";
case SHADER_FRAGMENT: return "FRAG";
case SHADER_COMPUTE: return "CL";
case MESA_SHADER_VERTEX: return "VERT";
case MESA_SHADER_FRAGMENT: return "FRAG";
case MESA_SHADER_COMPUTE: return "CL";
default:
unreachable("invalid type");
return NULL;