ac/surface: align DCC size for surfaces that use tile swizzle
Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks, which is greater than the previous open-coded alignment. Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -734,9 +734,16 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
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* complicated.
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* complicated.
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*/
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*/
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if (surf->dcc_size && config->info.levels > 1) {
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if (surf->dcc_size && config->info.levels > 1) {
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/* The smallest miplevels that are never compressed by DCC
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* still read the DCC buffer via TC if the base level uses DCC,
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* and for some reason the DCC buffer needs to be larger if
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* the miptree uses non-zero tile_swizzle. Otherwise there are
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* VM faults.
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*
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* "dcc_alignment * 4" was determined by trial and error.
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*/
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surf->dcc_size = align64(surf->surf_size >> 8,
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surf->dcc_size = align64(surf->surf_size >> 8,
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info->pipe_interleave_bytes *
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surf->dcc_alignment * 4);
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info->num_tile_pipes);
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}
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}
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/* Make sure HTILE covers the whole miptree, because the shader reads
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/* Make sure HTILE covers the whole miptree, because the shader reads
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