radeonsi: compile clear and copy buffer compute shaders on demand
same as all other shaders
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f139589069
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c605738113
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@ -111,12 +111,20 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
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sb[0].buffer_offset = dst_offset;
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sb[0].buffer_size = size;
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bool shader_dst_stream_policy = SI_COMPUTE_DST_CACHE_POLICY != L2_LRU;
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if (src) {
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sb[1].buffer = src;
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sb[1].buffer_offset = src_offset;
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sb[1].buffer_size = size;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 2, sb);
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if (!sctx->cs_copy_buffer) {
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sctx->cs_copy_buffer = si_create_dma_compute_shader(&sctx->b,
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SI_COMPUTE_COPY_DW_PER_THREAD,
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shader_dst_stream_policy, true);
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}
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ctx->bind_compute_state(ctx, sctx->cs_copy_buffer);
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} else {
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assert(clear_value_size >= 4 &&
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@ -127,6 +135,12 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
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sctx->cs_user_data[i] = clear_value[i % (clear_value_size / 4)];
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, sb);
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if (!sctx->cs_clear_buffer) {
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sctx->cs_clear_buffer = si_create_dma_compute_shader(&sctx->b,
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SI_COMPUTE_CLEAR_DW_PER_THREAD,
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shader_dst_stream_policy, false);
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}
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ctx->bind_compute_state(ctx, sctx->cs_clear_buffer);
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}
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@ -510,14 +510,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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if (sscreen->debug_flags & DBG(FORCE_DMA))
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sctx->b.resource_copy_region = sctx->dma_copy;
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bool dst_stream_policy = SI_COMPUTE_DST_CACHE_POLICY != L2_LRU;
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sctx->cs_clear_buffer = si_create_dma_compute_shader(&sctx->b,
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SI_COMPUTE_CLEAR_DW_PER_THREAD,
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dst_stream_policy, false);
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sctx->cs_copy_buffer = si_create_dma_compute_shader(&sctx->b,
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SI_COMPUTE_COPY_DW_PER_THREAD,
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dst_stream_policy, true);
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sctx->blitter = util_blitter_create(&sctx->b);
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if (sctx->blitter == NULL)
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goto fail;
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