aco: Introduce vgpr_limit to keep track of available VGPRs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
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@ -162,6 +162,11 @@ static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data
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* properly support subgroup shuffle like older generations (or wave32 mode), so we
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* emulate it here.
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*/
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if (!ctx->has_gfx10_wave64_bpermute) {
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ctx->has_gfx10_wave64_bpermute = true;
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ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
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ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
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}
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Temp lane_id = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u));
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lane_id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1), lane_id);
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@ -79,6 +79,7 @@ struct isel_context {
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std::unique_ptr<Temp[]> allocated;
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std::unordered_map<unsigned, std::array<Temp,4>> allocated_vec;
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Stage stage; /* Stage */
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bool has_gfx10_wave64_bpermute = false;
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struct {
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bool has_branch;
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uint16_t loop_nest_depth = 0;
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@ -1255,6 +1256,7 @@ setup_isel_context(Program* program,
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program->lds_alloc_granule = options->chip_class >= GFX7 ? 512 : 256;
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program->lds_limit = options->chip_class >= GFX7 ? 65536 : 32768;
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program->vgpr_limit = 256;
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if (options->chip_class >= GFX10) {
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program->physical_sgprs = 2560; /* doesn't matter as long as it's at least 128 * 20 */
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@ -1080,6 +1080,8 @@ public:
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uint16_t lds_alloc_granule;
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uint32_t lds_limit; /* in bytes */
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uint16_t vgpr_limit;
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uint16_t physical_sgprs;
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uint16_t sgpr_alloc_granule; /* minus one. must be power of two */
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uint16_t sgpr_limit;
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@ -244,7 +244,7 @@ void update_vgpr_sgpr_demand(Program* program, const RegisterDemand new_demand)
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const int16_t vgpr_alloc = std::max<int16_t>(4, (new_demand.vgpr + 3) & ~3);
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/* this won't compile, register pressure reduction necessary */
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if (new_demand.vgpr > 256 || new_demand.sgpr > program->sgpr_limit) {
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if (new_demand.vgpr > program->vgpr_limit || new_demand.sgpr > program->sgpr_limit) {
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program->num_waves = 0;
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program->max_reg_demand = new_demand;
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} else {
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@ -823,9 +823,6 @@ void lower_to_hw_instr(Program* program)
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assert(instr->operands[2].regClass() == v1); /* Indices x4 */
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assert(instr->operands[3].regClass() == v1); /* Input data */
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/* Shared VGPRs are allocated in groups of 8 */
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program->config->num_shared_vgprs = 8;
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PhysReg shared_vgpr_reg_lo = PhysReg(align(program->config->num_vgprs, 4) + 256);
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PhysReg shared_vgpr_reg_hi = PhysReg(shared_vgpr_reg_lo + 1);
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Operand compare = instr->operands[0];
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@ -668,7 +668,8 @@ PhysReg get_reg(ra_ctx& ctx,
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/* try using more registers */
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uint16_t max_addressible_sgpr = ctx.program->sgpr_limit;
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if (rc.type() == RegType::vgpr && ctx.program->max_reg_demand.vgpr < 256) {
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uint16_t max_addressible_vgpr = ctx.program->vgpr_limit;
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if (rc.type() == RegType::vgpr && ctx.program->max_reg_demand.vgpr < max_addressible_vgpr) {
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update_vgpr_sgpr_demand(ctx.program, RegisterDemand(ctx.program->max_reg_demand.vgpr + 1, ctx.program->max_reg_demand.sgpr));
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return get_reg(ctx, reg_file, rc, parallelcopies, instr);
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} else if (rc.type() == RegType::sgpr && ctx.program->max_reg_demand.sgpr < max_addressible_sgpr) {
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