radeonsi: swap DrawId and StartInstance SGPR locations

We need to change both values at the same time, so they need to be next
to each other.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7441>
This commit is contained in:
Marek Olšák 2020-11-02 05:53:26 -05:00 committed by Marge Bot
parent f14a05d618
commit c4310f70aa
4 changed files with 4 additions and 4 deletions

View File

@ -1129,8 +1129,8 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi, unsigned max_out
if (ctx->stage == MESA_SHADER_VERTEX) {
ret = si_insert_input_ptr(ctx, ret, ctx->args.base_vertex, 8 + SI_SGPR_BASE_VERTEX);
ret = si_insert_input_ptr(ctx, ret, ctx->args.start_instance, 8 + SI_SGPR_START_INSTANCE);
ret = si_insert_input_ptr(ctx, ret, ctx->args.draw_id, 8 + SI_SGPR_DRAWID);
ret = si_insert_input_ptr(ctx, ret, ctx->args.start_instance, 8 + SI_SGPR_START_INSTANCE);
ret = si_insert_input_ptr(ctx, ret, ctx->vertex_buffers, 8 + SI_VS_NUM_USER_SGPR);
for (unsigned i = 0; i < shader->selector->num_vbos_in_user_sgprs; i++) {

View File

@ -262,8 +262,8 @@ static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx)
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
if (!ctx->shader->is_gs_copy_shader) {
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.base_vertex);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.start_instance);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.draw_id);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.start_instance);
}
}

View File

@ -174,8 +174,8 @@ enum
/* all VS variants */
SI_SGPR_BASE_VERTEX = SI_NUM_VS_STATE_RESOURCE_SGPRS,
SI_SGPR_START_INSTANCE,
SI_SGPR_DRAWID,
SI_SGPR_START_INSTANCE,
SI_VS_NUM_USER_SGPR,
SI_SGPR_VS_BLIT_DATA = SI_SGPR_CONST_AND_SHADER_BUFFERS,

View File

@ -945,8 +945,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
info->drawid != sctx->last_drawid || sh_base_reg != sctx->last_sh_base_reg) {
radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
radeon_emit(cs, base_vertex);
radeon_emit(cs, info->start_instance);
radeon_emit(cs, info->drawid);
radeon_emit(cs, info->start_instance);
sctx->last_base_vertex = base_vertex;
sctx->last_start_instance = info->start_instance;