radv: Merge binning state generation with pm4 emission.
We don't need the pipeline state struct anymore. Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
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@ -2401,19 +2401,19 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
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}
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}
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static void
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static void
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radv_compute_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
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radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
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struct radv_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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{
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pipeline->graphics.bin.pa_sc_binner_cntl_0 =
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if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
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return;
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uint32_t pa_sc_binner_cntl_0 =
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S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
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S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
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S_028C44_DISABLE_START_OF_PRIM(1);
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S_028C44_DISABLE_START_OF_PRIM(1);
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pipeline->graphics.bin.db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
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uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
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if (!pipeline->device->pbb_allowed)
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return;
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VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
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VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo);
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if (!bin_size.width || !bin_size.height)
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return;
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unsigned context_states_per_bin; /* allowed range: [1, 6] */
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unsigned context_states_per_bin; /* allowed range: [1, 6] */
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unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
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unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
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@ -2434,7 +2434,8 @@ radv_compute_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipel
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unreachable("unhandled family while determining binning state.");
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unreachable("unhandled family while determining binning state.");
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}
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}
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pipeline->graphics.bin.pa_sc_binner_cntl_0 =
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if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
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pa_sc_binner_cntl_0 =
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S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
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S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
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S_028C44_BIN_SIZE_X(bin_size.width == 16) |
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S_028C44_BIN_SIZE_X(bin_size.width == 16) |
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S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
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S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
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@ -2445,9 +2446,12 @@ radv_compute_binning_state(struct radv_pipeline *pipeline, const VkGraphicsPipel
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S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_DISABLE_START_OF_PRIM(1) |
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S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
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S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
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S_028C44_OPTIMAL_BIN_SELECTION(1);
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S_028C44_OPTIMAL_BIN_SELECTION(1);
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}
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/* DFSM is not implemented yet */
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radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
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assert(!pipeline->device->dfsm_allowed);
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pa_sc_binner_cntl_0);
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radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
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db_dfsm_control);
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}
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}
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@ -2876,20 +2880,8 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_winsys_cs *cs,
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}
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}
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static void
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static void
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radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
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radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
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struct radv_pipeline *pipeline)
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const VkGraphicsPipelineCreateInfo *pCreateInfo)
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{
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if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
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return;
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radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
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pipeline->graphics.bin.pa_sc_binner_cntl_0);
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radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
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pipeline->graphics.bin.db_dfsm_control);
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}
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static void
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radv_pipeline_generate_pm4(struct radv_pipeline *pipeline)
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{
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{
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pipeline->cs.buf = malloc(4 * 256);
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pipeline->cs.buf = malloc(4 * 256);
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pipeline->cs.max_dw = 256;
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pipeline->cs.max_dw = 256;
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@ -2903,7 +2895,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline)
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radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline);
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radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline);
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radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
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radv_pipeline_generate_fragment_shader(&pipeline->cs, pipeline);
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radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
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radv_pipeline_generate_vgt_vertex_reuse(&pipeline->cs, pipeline);
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radv_pipeline_generate_binning_state(&pipeline->cs, pipeline);
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radv_pipeline_generate_binning_state(&pipeline->cs, pipeline, pCreateInfo);
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radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
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radeon_set_context_reg(&pipeline->cs, R_0286E8_SPI_TMPRING_SIZE,
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S_0286E8_WAVES(pipeline->max_waves) |
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S_0286E8_WAVES(pipeline->max_waves) |
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@ -3212,10 +3204,8 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
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radv_dump_pipeline_stats(device, pipeline);
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radv_dump_pipeline_stats(device, pipeline);
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}
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}
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radv_compute_binning_state(pipeline, pCreateInfo);
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result = radv_pipeline_scratch_init(device, pipeline);
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result = radv_pipeline_scratch_init(device, pipeline);
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radv_pipeline_generate_pm4(pipeline);
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radv_pipeline_generate_pm4(pipeline, pCreateInfo);
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return result;
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return result;
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}
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}
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@ -1203,11 +1203,6 @@ struct radv_vs_state {
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uint32_t vgt_reuse_off;
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uint32_t vgt_reuse_off;
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};
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};
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struct radv_binning_state {
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uint32_t pa_sc_binner_cntl_0;
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uint32_t db_dfsm_control;
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};
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#define SI_GS_PER_ES 128
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#define SI_GS_PER_ES 128
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struct radv_pipeline {
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struct radv_pipeline {
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@ -1238,7 +1233,6 @@ struct radv_pipeline {
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struct radv_tessellation_state tess;
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struct radv_tessellation_state tess;
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struct radv_gs_state gs;
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struct radv_gs_state gs;
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struct radv_vs_state vs;
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struct radv_vs_state vs;
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struct radv_binning_state bin;
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uint32_t db_shader_control;
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uint32_t db_shader_control;
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uint32_t shader_z_format;
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uint32_t shader_z_format;
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uint32_t spi_baryc_cntl;
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uint32_t spi_baryc_cntl;
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