freedreno: regenerate pm4 header, adjust code for new names
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Ilia Mirkin
parent
ffdcd51e66
commit
c3c8d48725
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@ -165,9 +165,9 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
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OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
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OUT_RING(ring, 0x00000000);
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OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
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OUT_RING(ring, CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
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CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
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CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
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OUT_RING(ring, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
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A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
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A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
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} else {
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OUT_PKT7(ring, CP_EXEC_CS, 4);
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OUT_RING(ring, 0x00000000);
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@ -105,7 +105,7 @@ fd5_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
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&batch->draw_patches);
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OUT_RELOC(ring, fd_resource(idx)->bo,
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index_offset, 0, 0);
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OUT_RING(ring, CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
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OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
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OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
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} else {
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OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
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@ -8,15 +8,15 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-11-18 20:43:22)
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- /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-11 01:04:14)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2017-11-18 20:48:10)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 15292 bytes, from 2017-11-19 20:45:26)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34349 bytes, from 2017-11-19 20:43:33)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-11-18 19:40:11)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112609 bytes, from 2017-11-19 04:47:10)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143017 bytes, from 2017-11-19 04:05:11)
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- /home/ilia/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-11-07 21:10:25)
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Copyright (C) 2013-2017 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -583,124 +583,151 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
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return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
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}
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#define REG_CP_DRAW_INDIRECT_0 0x00000000
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#define CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
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#define CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
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static inline uint32_t CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
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#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
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#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
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#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
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static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
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return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
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}
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#define CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
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#define CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
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static inline uint32_t CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
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#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
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#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
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static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
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return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
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}
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#define CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
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#define CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
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static inline uint32_t CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
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#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
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#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
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static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
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return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
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}
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#define CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
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#define CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
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static inline uint32_t CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
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#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
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#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
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static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
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{
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return ((val) << CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
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return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
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}
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#define CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
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#define CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
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static inline uint32_t CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
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#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
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#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
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static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
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{
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return ((val) << CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
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return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
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}
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#define REG_CP_DRAW_INDIRECT_1 0x00000001
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#define CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
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#define CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
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static inline uint32_t CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
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#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
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#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
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#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
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static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
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{
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return ((val) << CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
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return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
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}
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#define REG_CP_DRAW_INDIRECT_2 0x00000002
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#define CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
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#define CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
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static inline uint32_t CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
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#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
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#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
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#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
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static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
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{
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return ((val) << CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
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return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
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}
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#define REG_CP_DRAW_INDX_INDIRECT_0 0x00000000
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#define CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
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#define CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
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#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
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}
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#define CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
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#define CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
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static inline uint32_t CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
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}
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#define CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
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#define CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
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static inline uint32_t CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
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}
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#define CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
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#define CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
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static inline uint32_t CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
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}
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#define CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
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#define CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
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static inline uint32_t CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
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#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
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}
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#define REG_CP_DRAW_INDX_INDIRECT_1 0x00000001
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#define CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
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#define CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
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#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
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#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
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#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
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}
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#define REG_CP_DRAW_INDX_INDIRECT_2 0x00000002
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#define CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
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#define CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
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#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
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#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
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#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
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}
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#define REG_CP_DRAW_INDX_INDIRECT_3 0x00000003
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#define CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
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#define CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
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#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
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#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
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#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
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static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
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{
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return ((val) << CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
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return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
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}
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#define REG_CP_DRAW_INDX_INDIRECT_4 0x00000004
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#define CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
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#define CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
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static inline uint32_t CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
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#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
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#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
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#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_INDIRECT_5 0x00000005
|
||||
#define CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
|
||||
static inline uint32_t CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
||||
|
|
@ -1236,42 +1263,72 @@ static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
|
|||
return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_INDIRECT_0 0x00000000
|
||||
#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
|
||||
|
||||
#define REG_CP_EXEC_CS_INDIRECT_1 0x00000001
|
||||
#define CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
|
||||
|
||||
#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_INDIRECT_2 0x00000002
|
||||
#define CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
|
||||
#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
|
||||
}
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
|
||||
}
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_INDIRECT_3 0x00000003
|
||||
#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
|
||||
#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
|
||||
static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
|
||||
|
||||
#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
|
||||
}
|
||||
#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
|
||||
#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
|
||||
static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
|
||||
|
||||
#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
|
||||
}
|
||||
#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
|
||||
#define CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
|
||||
static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
|
||||
|
||||
#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
|
||||
}
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
|
||||
}
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue