freedreno/ir3: add test for delay slot calculation
Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
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@ -121,3 +121,14 @@ test('ir3_disasm',
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suite: ['freedreno'],
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suite: ['freedreno'],
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)
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test('ir3_delay_test',
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executable(
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'ir3_delay_test',
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'tests/delay.c',
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link_with: libfreedreno_ir3,
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dependencies: [idep_mesautil, idep_nir_headers],
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include_directories: [inc_freedreno, inc_include, inc_src, inc_mesa, inc_gallium],
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),
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suite: ['freedreno'],
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)
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@ -0,0 +1,167 @@
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/*
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* Copyright © 2020 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdio.h>
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#include "ir3.h"
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#include "ir3_compiler.h"
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#include "ir3_parser.h"
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/*
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* A test for delay-slot calculation. Each test specifies ir3 assembly
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* for one or more instructions and the last instruction that consumes
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* the previously produced values. And the expected number of delay
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* slots that would be needed before that last instruction. Any source
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* registers in the last instruction which are not written in a previous
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* instruction are not counted.
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*/
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#define TEST(n, ...) { # __VA_ARGS__, n }
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static const struct test {
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const char *asmstr;
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unsigned expected_delay;
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} tests[] = {
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TEST(6,
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add.f r0.x, r2.x, r2.y
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rsq r0.x, r0.x
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),
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TEST(3,
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mov.f32f32 r0.x, c0.x
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mov.f32f32 r0.y, c0.y
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add.f r0.x, r0.x, r0.y
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),
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TEST(2,
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mov.f32f32 r0.x, c0.x
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mov.f32f32 r0.y, c0.y
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mov.f32f32 r0.z, c0.z
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mad.f32 r0.x, r0.x, r0.y, r0.z
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),
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};
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static struct ir3 *
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parse_asm(struct ir3_compiler *c, const char *asmstr)
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{
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struct ir3_shader shader = {
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.type = MESA_SHADER_COMPUTE,
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.compiler = c,
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};
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struct ir3_shader_variant v = {
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.type = shader.type,
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.shader = &shader,
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};
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struct ir3_kernel_info info = {};
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FILE *in = fmemopen((void *)asmstr, strlen(asmstr), "r");
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struct ir3 *ir = ir3_parse(&v, &info, in);
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fclose(in);
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return ir;
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}
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static unsigned
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regn(struct ir3_register *reg)
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{
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unsigned regn = reg->num;
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if (reg->flags & IR3_REG_HALF)
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regn += MAX_REG;
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return regn;
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}
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/**
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* Super-cheezy into-ssa pass, doesn't handle flow control or anything
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* hard. Just enough to figure out the SSA srcs of the last instruction.
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*
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* Note that this is not clever enough to know how many src/dst there are
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* for various tex/mem instructions. But the rules for tex consuming alu
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* are the same as sfu consuming alu.
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*/
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static void
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regs_to_ssa(struct ir3 *ir)
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{
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struct ir3_instruction *regfile[2 * MAX_REG] = {};
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struct ir3_block *block =
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list_first_entry(&ir->block_list, struct ir3_block, node);
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foreach_instr (instr, &block->instr_list) {
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foreach_src (reg, instr) {
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if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED))
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continue;
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struct ir3_instruction *src = regfile[regn(reg)];
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if (!src)
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continue;
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reg->instr = src;
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reg->flags |= IR3_REG_SSA;
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}
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regfile[regn(instr->regs[0])] = instr;
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}
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}
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int
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main(int argc, char **argv)
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{
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struct ir3_compiler *c;
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int result = 0;
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c = ir3_compiler_create(NULL, 630);
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for (int i = 0; i < ARRAY_SIZE(tests); i++) {
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const struct test *test = &tests[i];
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struct ir3 *ir = parse_asm(c, test->asmstr);
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ir3_debug_print(ir, "AFTER PARSING");
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regs_to_ssa(ir);
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ir3_debug_print(ir, "AFTER REGS->SSA");
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struct ir3_block *block =
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list_first_entry(&ir->block_list, struct ir3_block, node);
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struct ir3_instruction *last =
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list_last_entry(&block->instr_list, struct ir3_instruction, node);
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/* The delay calc is expecting the instr to not yet be added to the
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* block, so remove it from the block so that it doesn't get counted
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* in the distance from assigner:
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*/
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list_delinit(&last->node);
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unsigned n = ir3_delay_calc(block, last, false, false);
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if (n != test->expected_delay) {
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printf("%d: FAIL: Expected delay %u, but got %u, for:\n%s\n",
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i, test->expected_delay, n, test->asmstr);
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result = -1;
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} else {
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printf("%d: PASS\n", i);
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}
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}
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return result;
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}
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