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i965/reg_allocate: Use make_reg_conflicts_transitive 

Instead of adding transitive conflicts as we go, we now add regular
conflicts and them make them all transitive at the end.  This reduces
screen creation time substantially on BDW.  The time spent in eglInitialize
is reduced from 27.78 ms/call to 9.92 ms/call in debug mode and from 13.15
ms/call to 4.54 ms/call in release mode (about 65% in either case).

Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jason Ekstrand 2015-08-15 09:50:11 -07:00
parent 9b49284c22
commit c3b21f2d56
2 changed files with 12 additions and 3 deletions
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10
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View File

@ -232,7 +232,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
for (int base_reg = j;
base_reg < j + (class_sizes[i] + 1) / 2;
base_reg++) {
ra_add_transitive_reg_conflict(regs, base_reg, reg);
ra_add_reg_conflict(regs, base_reg, reg);
}
reg++;
@ -246,7 +246,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
for (int base_reg = j;
base_reg < j + class_sizes[i];
base_reg++) {
ra_add_transitive_reg_conflict(regs, base_reg, reg);
ra_add_reg_conflict(regs, base_reg, reg);
}
reg++;
@ -255,6 +255,12 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
}
assert(reg == ra_reg_count);
/* Applying transitivity to all of the base registers gives us the
* appropreate register conflict relationships everywhere.
*/
for (int reg = 0; reg < base_reg_count; reg++)
ra_make_reg_conflicts_transitive(regs, reg);
/* Add a special class for aligned pairs, which we'll put delta_xy
* in on Gen <= 6 so that we can do PLN.
*/

5
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
View File

@ -140,7 +140,7 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
for (int base_reg = j;
base_reg < j + class_sizes[i];
base_reg++) {
ra_add_transitive_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg);
ra_add_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg);
}
reg++;
@ -158,6 +158,9 @@ brw_vec4_alloc_reg_set(struct brw_compiler *compiler)
}
assert(reg == ra_reg_count);
for (int reg = 0; reg < base_reg_count; reg++)
ra_make_reg_conflicts_transitive(compiler->vec4_reg_set.regs, reg);
ra_set_finalize(compiler->vec4_reg_set.regs, q_values);
for (int i = 0; i < MAX_VGRF_SIZE; i++)