radeonsi: support alloc a sparse texture
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14223>
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@ -136,6 +136,9 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
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if (res->b.b.flags & SI_RESOURCE_FLAG_DRIVER_INTERNAL)
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res->flags |= RADEON_FLAG_DRIVER_INTERNAL;
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if (res->b.b.flags & PIPE_RESOURCE_FLAG_SPARSE)
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res->flags |= RADEON_FLAG_SPARSE;
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/* For higher throughput and lower latency over PCIe assuming sequential access.
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* Only CP DMA and optimized compute benefit from this.
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* GFX8 and older don't support RADEON_FLAG_UNCACHED.
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@ -588,9 +591,6 @@ static struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
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si_init_resource_fields(sscreen, buf, templ->width0, alignment);
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if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
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buf->flags |= RADEON_FLAG_SPARSE;
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buf->b.buffer_id_unique = util_idalloc_mt_alloc(&sscreen->buffer_ids);
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if (!si_alloc_resource(sscreen, buf)) {
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@ -279,6 +279,14 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
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surface->u.gfx9.swizzle_mode = ADDR_SW_64KB_R_X;
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}
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if (ptex->flags & PIPE_RESOURCE_FLAG_SPARSE) {
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flags |=
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RADEON_SURF_PRT |
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RADEON_SURF_NO_FMASK |
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RADEON_SURF_NO_HTILE |
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RADEON_SURF_DISABLE_DCC;
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}
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surface->modifier = modifier;
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r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface);
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@ -996,6 +1004,9 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
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radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
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resource->gpu_address = plane0->buffer.gpu_address;
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} else if (!(surface->flags & RADEON_SURF_IMPORTED)) {
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if (base->flags & PIPE_RESOURCE_FLAG_SPARSE)
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resource->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
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/* Create the backing buffer. */
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si_init_resource_fields(sscreen, resource, alloc_size, alignment);
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@ -1266,6 +1277,8 @@ si_texture_create_with_modifier(struct pipe_screen *screen,
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is_flushed_depth, tc_compatible_htile))
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return NULL;
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plane_templ[i].nr_sparse_levels = surface[i].first_mip_tail_level;
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plane_offset[i] = align64(total_size, 1 << surface[i].surf_alignment_log2);
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total_size = plane_offset[i] + surface[i].total_size;
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max_alignment = MAX2(max_alignment, 1 << surface[i].surf_alignment_log2);
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