radeonsi/sqtt: export shader code to RGP
With these changes the shader code is visible in RGP. Vk pipeline feature is emulated using si_update_shaders: when shaders are updated we compute a sha1 of their code and use it as a pipeline hash. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9277>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
Marge Bot
parent
729d3eb0e0
commit
c276bde34a
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@ -1580,6 +1580,10 @@ void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *r
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uint32_t vertex_offset_user_data,
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uint32_t instance_offset_user_data,
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uint32_t draw_index_user_data);
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bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address);
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bool si_sqtt_pipeline_is_registered(struct ac_thread_trace_data *thread_trace_data,
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uint64_t pipeline_hash);
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void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash);
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void
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si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
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enum rgp_sqtt_marker_event_type api_type,
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@ -582,6 +582,15 @@ si_init_thread_trace(struct si_context *sctx)
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if (!si_thread_trace_init_bo(sctx))
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return false;
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list_inithead(&sctx->thread_trace->rgp_pso_correlation.record);
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simple_mtx_init(&sctx->thread_trace->rgp_pso_correlation.lock, mtx_plain);
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list_inithead(&sctx->thread_trace->rgp_loader_events.record);
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simple_mtx_init(&sctx->thread_trace->rgp_loader_events.lock, mtx_plain);
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list_inithead(&sctx->thread_trace->rgp_code_object.record);
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simple_mtx_init(&sctx->thread_trace->rgp_code_object.lock, mtx_plain);
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si_thread_trace_init_cs(sctx);
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sctx->sqtt_next_event = EventInvalid;
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@ -592,14 +601,48 @@ si_init_thread_trace(struct si_context *sctx)
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void
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si_destroy_thread_trace(struct si_context *sctx)
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{
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struct si_screen *sscreen = sctx->screen;
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struct si_screen *sscreen = sctx->screen;
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struct pb_buffer *bo = sctx->thread_trace->bo;
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pb_reference(&bo, NULL);
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if (sctx->thread_trace->trigger_file)
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free(sctx->thread_trace->trigger_file);
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sscreen->ws->cs_destroy(sctx->thread_trace->start_cs[RING_GFX]);
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sscreen->ws->cs_destroy(sctx->thread_trace->stop_cs[RING_GFX]);
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struct rgp_pso_correlation *pso_correlation = &sctx->thread_trace->rgp_pso_correlation;
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struct rgp_loader_events *loader_events = &sctx->thread_trace->rgp_loader_events;
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struct rgp_code_object *code_object = &sctx->thread_trace->rgp_code_object;
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list_for_each_entry_safe(struct rgp_pso_correlation_record, record,
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&pso_correlation->record, list) {
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list_del(&record->list);
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free(record);
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}
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simple_mtx_destroy(&sctx->thread_trace->rgp_pso_correlation.lock);
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list_for_each_entry_safe(struct rgp_loader_events_record, record,
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&loader_events->record, list) {
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list_del(&record->list);
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free(record);
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}
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simple_mtx_destroy(&sctx->thread_trace->rgp_loader_events.lock);
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list_for_each_entry_safe(struct rgp_code_object_record, record,
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&code_object->record, list) {
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uint32_t mask = record->shader_stages_mask;
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int i;
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/* Free the disassembly. */
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while (mask) {
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i = u_bit_scan(&mask);
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free(record->shader_data[i].code);
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}
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list_del(&record->list);
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free(record);
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}
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simple_mtx_destroy(&sctx->thread_trace->rgp_code_object.lock);
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free(sctx->thread_trace);
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sctx->thread_trace = NULL;
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}
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@ -634,6 +677,11 @@ si_handle_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs)
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sctx->thread_trace_enabled = true;
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sctx->thread_trace->start_frame = -1;
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/* Force shader update to make sure si_sqtt_describe_pipeline_bind is called
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* for the current "pipeline".
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*/
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sctx->do_update_shaders = true;
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}
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} else {
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struct ac_thread_trace thread_trace = {0};
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@ -787,3 +835,156 @@ si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
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si_emit_thread_trace_userdata(sctx, rcs, buffer, sizeof(marker) / 4 + marker.length / 4);
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}
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}
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bool
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si_sqtt_pipeline_is_registered(struct ac_thread_trace_data *thread_trace_data,
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uint64_t pipeline_hash)
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{
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simple_mtx_lock(&thread_trace_data->rgp_pso_correlation.lock);
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list_for_each_entry_safe(struct rgp_pso_correlation_record, record,
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&thread_trace_data->rgp_pso_correlation.record, list) {
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if (record->pipeline_hash[0] == pipeline_hash) {
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simple_mtx_unlock(&thread_trace_data->rgp_pso_correlation.lock);
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return true;
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}
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}
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simple_mtx_unlock(&thread_trace_data->rgp_pso_correlation.lock);
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return false;
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}
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static enum rgp_hardware_stages
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si_sqtt_pipe_to_rgp_shader_stage(struct si_shader_key* key, enum pipe_shader_type stage)
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{
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switch (stage) {
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case PIPE_SHADER_VERTEX:
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if (key->as_ls)
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return RGP_HW_STAGE_LS;
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else if (key->as_es)
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return RGP_HW_STAGE_ES;
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else if (key->as_ngg)
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return RGP_HW_STAGE_GS;
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else
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return RGP_HW_STAGE_VS;
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case PIPE_SHADER_TESS_CTRL:
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return RGP_HW_STAGE_HS;
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case PIPE_SHADER_TESS_EVAL:
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if (key->as_es)
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return RGP_HW_STAGE_ES;
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else if (key->as_ngg)
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return RGP_HW_STAGE_GS;
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else
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return RGP_HW_STAGE_VS;
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case PIPE_SHADER_GEOMETRY:
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return RGP_HW_STAGE_GS;
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case PIPE_SHADER_FRAGMENT:
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return RGP_HW_STAGE_PS;
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case PIPE_SHADER_COMPUTE:
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return RGP_HW_STAGE_CS;
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default:
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unreachable("invalid mesa shader stage");
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}
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}
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static bool
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si_sqtt_add_code_object(struct si_context* sctx,
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uint64_t pipeline_hash)
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{
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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struct rgp_code_object *code_object = &thread_trace_data->rgp_code_object;
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struct rgp_code_object_record *record;
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record = malloc(sizeof(struct rgp_code_object_record));
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if (!record)
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return false;
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record->shader_stages_mask = 0;
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record->num_shaders_combined = 0;
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record->pipeline_hash[0] = pipeline_hash;
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record->pipeline_hash[1] = pipeline_hash;
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for (unsigned i = 0; i < PIPE_SHADER_TYPES; i++) {
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if (i != PIPE_SHADER_COMPUTE) {
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if (!sctx->shaders[i].cso || !sctx->shaders[i].current)
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continue;
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} else {
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/* TODO */
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continue;
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}
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struct si_shader *shader = sctx->shaders[i].current;
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enum rgp_hardware_stages hw_stage = si_sqtt_pipe_to_rgp_shader_stage(&shader->key, i);
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uint8_t *code = malloc(shader->binary.uploaded_code_size);
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if (!code) {
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free(record);
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return false;
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}
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memcpy(code, shader->binary.uploaded_code, shader->binary.uploaded_code_size);
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uint64_t va = shader->bo->gpu_address;
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record->shader_data[i].hash[0] = _mesa_hash_data(code, shader->binary.uploaded_code_size);
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record->shader_data[i].hash[1] = record->shader_data[i].hash[0];
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record->shader_data[i].code_size = shader->binary.uploaded_code_size;
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record->shader_data[i].code = code;
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record->shader_data[i].vgpr_count = shader->config.num_vgprs;
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record->shader_data[i].sgpr_count = shader->config.num_sgprs;
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record->shader_data[i].base_address = va & 0xffffffffffff;
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record->shader_data[i].elf_symbol_offset = 0;
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record->shader_data[i].hw_stage = hw_stage;
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record->shader_data[i].is_combined = false;
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record->shader_stages_mask |= (1 << i);
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record->num_shaders_combined++;
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}
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simple_mtx_lock(&code_object->lock);
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list_addtail(&record->list, &code_object->record);
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code_object->record_count++;
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simple_mtx_unlock(&code_object->lock);
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return true;
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}
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bool
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si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address)
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{
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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assert (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_hash));
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bool result = ac_sqtt_add_pso_correlation(thread_trace_data, pipeline_hash);
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if (!result)
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return false;
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result = ac_sqtt_add_code_object_loader_event(thread_trace_data, pipeline_hash, base_address);
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if (!result)
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return false;
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return si_sqtt_add_code_object(sctx, pipeline_hash);
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}
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void
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si_sqtt_describe_pipeline_bind(struct si_context* sctx,
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uint64_t pipeline_hash)
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{
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struct rgp_sqtt_marker_pipeline_bind marker = {0};
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struct radeon_cmdbuf *cs = &sctx->gfx_cs;
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if (likely(!sctx->thread_trace_enabled)) {
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return;
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}
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marker.identifier = RGP_SQTT_MARKER_IDENTIFIER_BIND_PIPELINE;
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marker.cb_id = 0;
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marker.bind_point = 0 /* VK_PIPELINE_BIND_POINT_GRAPHICS */;
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marker.api_pso_hash[0] = pipeline_hash;
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marker.api_pso_hash[1] = pipeline_hash >> 32;
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si_emit_thread_trace_userdata(sctx, cs, &marker, sizeof(marker) / 4);
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}
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@ -4161,6 +4161,31 @@ bool si_update_shaders(struct si_context *sctx)
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}
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}
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if (sctx->screen->debug_flags & DBG(SQTT)) {
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/* Pretend the bound shaders form a vk pipeline */
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uint32_t pipeline_code_hash = 0;
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uint64_t base_address = ~0;
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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pipeline_code_hash = _mesa_hash_data_with_seed(
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shader->binary.elf_buffer,
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shader->binary.elf_size,
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pipeline_code_hash);
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base_address = MIN2(base_address,
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shader->bo->gpu_address);
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}
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}
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struct ac_thread_trace_data *thread_trace_data = sctx->thread_trace;
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if (!si_sqtt_pipeline_is_registered(thread_trace_data, pipeline_code_hash)) {
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si_sqtt_register_pipeline(sctx, pipeline_code_hash, base_address);
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}
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si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash);
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}
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if (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, hs) ||
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si_pm4_state_enabled_and_changed(sctx, es) || si_pm4_state_enabled_and_changed(sctx, gs) ||
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si_pm4_state_enabled_and_changed(sctx, vs) || si_pm4_state_enabled_and_changed(sctx, ps)) {
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