radeonsi: add debug flags for dumping tessellation shaders
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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3ce91c727f
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@ -333,6 +333,8 @@ static const struct debug_named_value common_debug_options[] = {
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{ "gs", DBG_GS, "Print geometry shaders" },
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{ "ps", DBG_PS, "Print pixel shaders" },
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{ "cs", DBG_CS, "Print compute shaders" },
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{ "tcs", DBG_TCS, "Print tessellation control shaders" },
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{ "tes", DBG_TES, "Print tessellation evaluation shaders" },
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/* features */
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{ "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
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@ -956,6 +958,10 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen,
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switch (tgsi_get_processor_type(tokens)) {
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case TGSI_PROCESSOR_VERTEX:
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return (rscreen->debug_flags & DBG_VS) != 0;
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case TGSI_PROCESSOR_TESS_CTRL:
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return (rscreen->debug_flags & DBG_TCS) != 0;
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case TGSI_PROCESSOR_TESS_EVAL:
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return (rscreen->debug_flags & DBG_TES) != 0;
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case TGSI_PROCESSOR_GEOMETRY:
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return (rscreen->debug_flags & DBG_GS) != 0;
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case TGSI_PROCESSOR_FRAGMENT:
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@ -79,16 +79,18 @@
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#define DBG_GS (1 << 7)
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#define DBG_PS (1 << 8)
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#define DBG_CS (1 << 9)
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#define DBG_TCS (1 << 10)
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#define DBG_TES (1 << 11)
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/* features */
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#define DBG_NO_ASYNC_DMA (1 << 10)
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#define DBG_NO_HYPERZ (1 << 11)
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#define DBG_NO_DISCARD_RANGE (1 << 12)
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#define DBG_NO_2D_TILING (1 << 13)
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#define DBG_NO_TILING (1 << 14)
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#define DBG_SWITCH_ON_EOP (1 << 15)
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#define DBG_FORCE_DMA (1 << 16)
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#define DBG_PRECOMPILE (1 << 17)
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#define DBG_INFO (1 << 18)
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#define DBG_NO_ASYNC_DMA (1 << 12)
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#define DBG_NO_HYPERZ (1 << 13)
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#define DBG_NO_DISCARD_RANGE (1 << 14)
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#define DBG_NO_2D_TILING (1 << 15)
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#define DBG_NO_TILING (1 << 16)
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#define DBG_SWITCH_ON_EOP (1 << 17)
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#define DBG_FORCE_DMA (1 << 18)
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#define DBG_PRECOMPILE (1 << 19)
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#define DBG_INFO (1 << 20)
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/* The maximum allowed bit is 20. */
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#define R600_MAP_BUFFER_ALIGNMENT 64
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