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nv50,nvc0: make sure there's pushbuf space and that we ref the bo early 

First off, we can't flush in the middle of a command. Secondly
requesting the extra push space might cause a flush to happen. If that
flush happens, we'd have to do the PUSH_REFN again. So instead do
PUSH_REFN after the push space request. This helps avoid rare crashes
with supertuxkart in libdrm due to assertion failures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Ilia Mirkin 2015-12-31 20:33:15 -05:00
parent 33a415310b
commit c1d14c6817
4 changed files with 5 additions and 6 deletions
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2
src/gallium/drivers/nouveau/nv50/nv50_vbo.c
View File

@ -636,8 +636,8 @@ nv50_draw_elements(struct nv50_context *nv50, bool shorten,
BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1);
PUSH_DATA (push, prim);
PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
nouveau_pushbuf_space(push, 8, 0, 1);
PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
switch (index_size) {
case 4:

1
src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
View File

@ -473,7 +473,6 @@ nvc0_hw_query_pushbuf_submit(struct nouveau_pushbuf *push,
#define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
PUSH_REFN(push, hq->bo, NOUVEAU_BO_RD | NOUVEAU_BO_GART);
nouveau_pushbuf_space(push, 0, 0, 1);
nouveau_pushbuf_data(push, hq->bo, hq->offset + result_offset, 4 |
NVC0_IB_ENTRY_1_NO_PREFETCH);
}

1
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
View File

@ -317,6 +317,7 @@ nvc0_tfb_validate(struct nvc0_context *nvc0)
if (!targ->clean)
nvc0_hw_query_fifo_wait(push, nvc0_query(targ->pq));
nouveau_pushbuf_space(push, 0, 0, 1);
BEGIN_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 5);
PUSH_DATA (push, 1);
PUSH_DATAh(push, buf->address + targ->pipe.buffer_offset);

7
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
View File

@ -787,7 +787,7 @@ nvc0_draw_stream_output(struct nvc0_context *nvc0,
}
while (num_instances--) {
PUSH_SPACE(push, 8);
nouveau_pushbuf_space(push, 9, 0, 1);
BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1);
PUSH_DATA (push, mode);
BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1);
@ -822,7 +822,8 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
BEGIN_NVC0(push, NVC0_3D(CB_POS), 1);
PUSH_DATA (push, 256 + 128);
PUSH_SPACE(push, 8);
nouveau_pushbuf_space(push, 8, 0, 1);
PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
if (info->indexed) {
assert(nvc0->idxbuf.buffer);
assert(nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer));
@ -840,8 +841,6 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
}
PUSH_DATA(push, nvc0_prim_gl(info->mode));
#define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain);
nouveau_pushbuf_space(push, 0, 0, 1);
nouveau_pushbuf_data(push,
buf->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | size);
}