iris: Handle importing aux-enabled surfaces on TGL
Ensure main surfaces are properly 64KB-aligned (as suggested by Jordan) and map the main surface addresses to aux surface addresses on import. v2. Add a Bspec quote. (Sagar) v3. Add a bit more to the Bspec comment. (Ken) Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
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@ -1407,7 +1407,20 @@ iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd,
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bo->reusable = false;
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bo->external = true;
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bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
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bo->gtt_offset = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 1);
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/* From the Bspec, Memory Compression - Gen12:
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*
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* The base address for the surface has to be 64K page aligned and the
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* surface is expected to be padded in the virtual domain to be 4 4K
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* pages.
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*
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* The dmabuf may contain a compressed surface. Align the BO to 64KB just
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* in case. We always align to 64KB even on platforms where we don't need
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* to, because it's a fairly reasonable thing to do anyway.
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*/
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bo->gtt_offset =
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vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 64 * 1024);
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bo->gem_handle = handle;
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_mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
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@ -766,6 +766,8 @@ iris_resource_finish_aux_import(struct pipe_screen *pscreen,
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iris_resource_destroy(&screen->base, res->base.next);
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res->base.next = NULL;
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map_aux_addresses(screen, res);
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}
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static struct pipe_resource *
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