iris: Handle importing aux-enabled surfaces on TGL

Ensure main surfaces are properly 64KB-aligned (as suggested by Jordan)
and map the main surface addresses to aux surface addresses on import.

v2. Add a Bspec quote. (Sagar)
v3. Add a bit more to the Bspec comment. (Ken)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>

src/gallium/drivers/iris/iris_bufmgr.c

@@ -1407,7 +1407,20 @@ iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd,
    bo->reusable = false;
    bo->external = true;
    bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
-   bo->gtt_offset = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 1);
+
+   /* From the Bspec, Memory Compression - Gen12:
+    *
+    *    The base address for the surface has to be 64K page aligned and the
+    *    surface is expected to be padded in the virtual domain to be 4 4K
+    *    pages.
+    *
+    * The dmabuf may contain a compressed surface. Align the BO to 64KB just
+    * in case. We always align to 64KB even on platforms where we don't need
+    * to, because it's a fairly reasonable thing to do anyway.
+    */
+   bo->gtt_offset =
+      vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 64 * 1024);
+
    bo->gem_handle = handle;
    _mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
 

src/gallium/drivers/iris/iris_resource.c

@@ -766,6 +766,8 @@ iris_resource_finish_aux_import(struct pipe_screen *pscreen,
 
    iris_resource_destroy(&screen->base, res->base.next);
    res->base.next = NULL;
+
+   map_aux_addresses(screen, res);
 }
 
 static struct pipe_resource *