intel: devinfo: add helper functions to fill fusing masks values
There are a couple of ways we can get the fusing information from the
kernel :
- Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK
parameters
- Through the new DRM_IOCTL_I915_QUERY by requesting the
DRM_I915_QUERY_TOPOLOGY_INFO
The second method is more accurate and also gives us the EUs fusing
masks. It's also a requirement for CNL as this platform has asymetric
subslices and the first method SUBSLICE_MASK value is assumed uniform
across slices.
v2: Change gen_device_info_update_from_masks() to generate topology
and call into gen_device_info_update_from_topology (Lionel/Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Lionel Landwerlin
parent
2d26c99933
commit
c1900f5b0f
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@ -28,8 +28,11 @@
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#include <unistd.h>
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#include "gen_device_info.h"
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#include "compiler/shader_enums.h"
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#include "util/bitscan.h"
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#include "util/macros.h"
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#include <i915_drm.h>
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/**
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* Get the PCI ID for the device name.
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*
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@ -925,6 +928,129 @@ fill_masks(struct gen_device_info *devinfo)
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}
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}
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void
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gen_device_info_update_from_masks(struct gen_device_info *devinfo,
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uint32_t slice_mask,
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uint32_t subslice_mask,
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uint32_t n_eus)
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{
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struct {
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struct drm_i915_query_topology_info base;
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uint8_t data[100];
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} topology;
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assert((slice_mask & 0xff) == slice_mask);
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memset(&topology, 0, sizeof(topology));
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topology.base.max_slices = util_last_bit(slice_mask);
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topology.base.max_subslices = util_last_bit(subslice_mask);
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topology.base.subslice_offset = DIV_ROUND_UP(topology.base.max_slices, 8);
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topology.base.subslice_stride = DIV_ROUND_UP(topology.base.max_subslices, 8);
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uint32_t n_subslices = __builtin_popcount(slice_mask) *
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__builtin_popcount(subslice_mask);
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uint32_t num_eu_per_subslice = DIV_ROUND_UP(n_eus, n_subslices);
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uint32_t eu_mask = (1U << num_eu_per_subslice) - 1;
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topology.base.eu_offset = topology.base.subslice_offset +
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DIV_ROUND_UP(topology.base.max_subslices, 8);
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topology.base.eu_stride = DIV_ROUND_UP(num_eu_per_subslice, 8);
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/* Set slice mask in topology */
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for (int b = 0; b < topology.base.subslice_offset; b++)
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topology.base.data[b] = (slice_mask >> (b * 8)) & 0xff;
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for (int s = 0; s < topology.base.max_slices; s++) {
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/* Set subslice mask in topology */
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for (int b = 0; b < topology.base.subslice_stride; b++) {
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int subslice_offset = topology.base.subslice_offset +
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s * topology.base.subslice_stride + b;
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topology.base.data[subslice_offset] = (subslice_mask >> (b * 8)) & 0xff;
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}
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/* Set eu mask in topology */
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for (int ss = 0; ss < topology.base.max_subslices; ss++) {
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for (int b = 0; b < topology.base.eu_stride; b++) {
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int eu_offset = topology.base.eu_offset +
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(s * topology.base.max_subslices + ss) * topology.base.eu_stride + b;
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topology.base.data[eu_offset] = (eu_mask >> (b * 8)) & 0xff;
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}
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}
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}
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gen_device_info_update_from_topology(devinfo, &topology.base);
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}
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static void
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reset_masks(struct gen_device_info *devinfo)
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{
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devinfo->subslice_slice_stride = 0;
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devinfo->eu_subslice_stride = 0;
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devinfo->eu_slice_stride = 0;
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devinfo->num_slices = 0;
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devinfo->num_eu_per_subslice = 0;
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memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
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memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
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memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
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memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
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}
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void
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gen_device_info_update_from_topology(struct gen_device_info *devinfo,
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const struct drm_i915_query_topology_info *topology)
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{
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reset_masks(devinfo);
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devinfo->subslice_slice_stride = topology->subslice_stride;
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devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
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devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
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assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
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memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
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devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
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uint32_t subslice_mask_len =
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topology->max_slices * topology->subslice_stride;
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assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
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memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
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subslice_mask_len);
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uint32_t n_subslices = 0;
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for (int s = 0; s < topology->max_slices; s++) {
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if ((devinfo->slice_masks & (1UL << s)) == 0)
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continue;
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for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
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devinfo->num_subslices[s] +=
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__builtin_popcount(devinfo->subslice_masks[b]);
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}
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n_subslices += devinfo->num_subslices[s];
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}
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uint32_t eu_mask_len =
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topology->eu_stride * topology->max_subslices * topology->max_slices;
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assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
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memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
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uint32_t n_eus = 0;
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for (int b = 0; b < eu_mask_len; b++)
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n_eus += __builtin_popcount(devinfo->eu_masks[b]);
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/* We expect the total number of EUs to be uniformly distributed throughout
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* the subslices.
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*/
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assert((n_eus % n_subslices) == 0);
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devinfo->num_eu_per_subslice = n_eus / n_subslices;
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}
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bool
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gen_get_device_info(int devid, struct gen_device_info *devinfo)
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{
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@ -34,6 +34,8 @@
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extern "C" {
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#endif
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struct drm_i915_query_topology_info;
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#define GEN_DEVICE_MAX_SLICES (6) /* Maximum on gen10 */
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#define GEN_DEVICE_MAX_SUBSLICES (8) /* Maximum on gen11 */
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#define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (10) /* Maximum on Haswell */
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@ -121,7 +123,9 @@ struct gen_device_info
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unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
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/**
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* Number of EU per subslice.
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* Upper bound of number of EU per subslice (some SKUs might have just 1 EU
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* fused across all subslices, like 47 EUs, in which case this number won't
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* be acurate for one subslice).
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*/
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unsigned num_eu_per_subslice;
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@ -248,6 +252,15 @@ int gen_device_name_to_pci_device_id(const char *name);
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bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
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const char *gen_get_device_name(int devid);
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/* Used with SLICE_MASK/SUBSLICE_MASK values from DRM_I915_GETPARAM. */
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void gen_device_info_update_from_masks(struct gen_device_info *devinfo,
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uint32_t slice_mask,
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uint32_t subslice_mask,
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uint32_t n_eus);
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/* Used with DRM_IOCTL_I915_QUERY & DRM_I915_QUERY_TOPOLOGY_INFO. */
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void gen_device_info_update_from_topology(struct gen_device_info *devinfo,
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const struct drm_i915_query_topology_info *topology);
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#ifdef __cplusplus
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}
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#endif
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