nvc0/ir: all short immediates are sign-extended, adjust LIMM test
Some analysis suggests that all short immediates are sign-extended. The insnCanLoad logic already accounted for this, but we could still pick the wrong form when emitting actual instructions that support both short and long immediates (with the long form usually having additional restrictions that insnCanLoad should be aware of). This also reverses a bunch of commits that had previously "worked around" this issue in various emitters: 9c63224540ef: gm107/ir: make use of ADD32I for all immediates 83a4f28dc27b: gm107/ir: make use of LOP32I for all immediates b84c97587b4a: gm107/ir: make use of IMUL32I for all immediates d30768025a22: gk110/ir: make use of IMUL32I for all immediates as well as the original import for UMUL in the nvc0 emitter. Reported-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Tested-by: Karol Herbst <kherbst@redhat.com>
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@ -207,7 +207,11 @@ bool CodeEmitterGK110::isLIMM(const ValueRef& ref, DataType ty, bool mod)
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{
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const ImmediateValue *imm = ref.get()->asImm();
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return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
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if (ty == TYPE_F32)
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return imm && imm->reg.data.u32 & 0xfff;
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else
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return imm && (imm->reg.data.s32 > 0x7ffff ||
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imm->reg.data.s32 < -0x80000);
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}
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void
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@ -342,7 +346,7 @@ CodeEmitterGK110::setShortImmediate(const Instruction *i, const int s)
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code[1] |= ((u64 & 0x7fe0000000000000ULL) >> 53);
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code[1] |= ((u64 & 0x8000000000000000ULL) >> 36);
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} else {
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assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
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assert((u32 & 0xfff80000) == 0 || (u32 & 0xfff80000) == 0xfff80000);
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code[0] |= (u32 & 0x001ff) << 23;
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code[1] |= (u32 & 0x7fe00) >> 9;
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code[1] |= (u32 & 0x80000) << 8;
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@ -633,7 +637,7 @@ CodeEmitterGK110::emitIMUL(const Instruction *i)
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assert(!i->src(0).mod.neg() && !i->src(1).mod.neg());
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assert(!i->src(0).mod.abs() && !i->src(1).mod.abs());
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if (i->src(1).getFile() == FILE_IMMEDIATE) {
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if (isLIMM(i->src(1), TYPE_S32)) {
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emitForm_L(i, 0x280, 2, Modifier(0));
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if (i->subOp == NV50_IR_SUBOP_MUL_HIGH)
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@ -321,14 +321,10 @@ CodeEmitterGM107::longIMMD(const ValueRef &ref)
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{
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if (ref.getFile() == FILE_IMMEDIATE) {
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const ImmediateValue *imm = ref.get()->asImm();
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if (isFloatType(insn->sType)) {
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if ((imm->reg.data.u32 & 0x00000fff) != 0x00000000)
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return true;
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} else {
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if ((imm->reg.data.u32 & 0xfff00000) != 0x00000000 &&
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(imm->reg.data.u32 & 0xfff00000) != 0xfff00000)
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return true;
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}
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if (isFloatType(insn->sType))
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return imm->reg.data.u32 & 0xfff;
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else
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return imm->reg.data.s32 > 0x7ffff || imm->reg.data.s32 < -0x80000;
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}
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return false;
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}
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@ -346,8 +342,9 @@ CodeEmitterGM107::emitIMMD(int pos, int len, const ValueRef &ref)
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} else if (insn->sType == TYPE_F64) {
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assert(!(imm->reg.data.u64 & 0x00000fffffffffffULL));
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val = imm->reg.data.u64 >> 44;
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} else {
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assert(!(val & 0xfff80000) || (val & 0xfff80000) == 0xfff80000);
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}
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assert(!(val & 0xfff00000) || (val & 0xfff00000) == 0xfff00000);
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emitField( 56, 1, (val & 0x80000) >> 19);
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emitField(pos, len, (val & 0x7ffff));
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} else {
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@ -1658,7 +1655,7 @@ CodeEmitterGM107::emitLOP()
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break;
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}
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if (insn->src(1).getFile() != FILE_IMMEDIATE) {
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if (!longIMMD(insn->src(1))) {
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switch (insn->src(1).getFile()) {
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case FILE_GPR:
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emitInsn(0x5c400000);
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@ -1731,7 +1728,7 @@ CodeEmitterGM107::emitNOT()
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void
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CodeEmitterGM107::emitIADD()
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{
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if (insn->src(1).getFile() != FILE_IMMEDIATE) {
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if (!longIMMD(insn->src(1))) {
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switch (insn->src(1).getFile()) {
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case FILE_GPR:
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emitInsn(0x5c100000);
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@ -1773,7 +1770,7 @@ CodeEmitterGM107::emitIADD()
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void
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CodeEmitterGM107::emitIMUL()
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{
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if (insn->src(1).getFile() != FILE_IMMEDIATE) {
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if (!longIMMD(insn->src(1))) {
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switch (insn->src(1).getFile()) {
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case FILE_GPR:
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emitInsn(0x5c380000);
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@ -213,7 +213,11 @@ bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
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{
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const ImmediateValue *imm = ref.get()->asImm();
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return imm && (imm->reg.data.u32 & ((ty == TYPE_F32) ? 0xfff : 0xfff00000));
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if (ty == TYPE_F32)
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return imm && imm->reg.data.u32 & 0xfff;
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else
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return imm && (imm->reg.data.s32 > 0x7ffff ||
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imm->reg.data.s32 < -0x80000);
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}
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void
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@ -352,7 +356,7 @@ CodeEmitterNVC0::setImmediate(const Instruction *i, const int s)
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} else
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if ((code[0] & 0xf) == 0x3 || (code[0] & 0xf) == 4) {
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// integer immediate
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assert((u32 & 0xfff00000) == 0 || (u32 & 0xfff00000) == 0xfff00000);
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assert((u32 & 0xfff80000) == 0 || (u32 & 0xfff80000) == 0xfff80000);
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assert(!(code[1] & 0xc000));
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u32 &= 0xfffff;
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code[0] |= (u32 & 0x3f) << 26;
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@ -641,7 +645,7 @@ void
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CodeEmitterNVC0::emitUMUL(const Instruction *i)
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{
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if (i->encSize == 8) {
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if (i->src(1).getFile() == FILE_IMMEDIATE) {
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if (isLIMM(i->src(1), TYPE_U32)) {
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emitForm_A(i, HEX64(10000000, 00000002));
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} else {
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emitForm_A(i, HEX64(50000000, 00000003));
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@ -2069,7 +2073,7 @@ CodeEmitterNVC0::emitMOV(const Instruction *i)
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assert(!(imm & 0x000fffff));
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code[0] = 0x00000318 | imm;
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} else {
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assert(imm < 0x800 || ((int32_t)imm >= -0x800));
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assert(imm < 0x800 && ((int32_t)imm >= -0x800));
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code[0] = 0x00000118 | (imm << 20);
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}
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} else {
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