i965: Make a common backend_reg class.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
parent
9377b189f7
commit
c019105f37
|
@ -63,7 +63,7 @@ namespace brw {
|
||||||
class fs_live_variables;
|
class fs_live_variables;
|
||||||
}
|
}
|
||||||
|
|
||||||
class fs_reg {
|
class fs_reg : public backend_reg {
|
||||||
public:
|
public:
|
||||||
DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
|
DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
|
||||||
|
|
||||||
|
@ -90,36 +90,14 @@ public:
|
||||||
/** Smear a channel of the reg to all channels. */
|
/** Smear a channel of the reg to all channels. */
|
||||||
fs_reg &set_smear(unsigned subreg);
|
fs_reg &set_smear(unsigned subreg);
|
||||||
|
|
||||||
/** Register file: GRF, MRF, IMM. */
|
|
||||||
enum register_file file;
|
|
||||||
/** Register type. BRW_REGISTER_TYPE_* */
|
|
||||||
uint8_t type;
|
|
||||||
/**
|
|
||||||
* Register number. For MRF, it's the hardware register. For
|
|
||||||
* GRF, it's a virtual register number until register allocation
|
|
||||||
*/
|
|
||||||
uint16_t reg;
|
|
||||||
/**
|
|
||||||
* Offset from the start of the contiguous register block.
|
|
||||||
*
|
|
||||||
* For pre-register-allocation GRFs, this is in units of a float per pixel
|
|
||||||
* (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
|
|
||||||
* For uniforms, this is in units of 1 float.
|
|
||||||
*/
|
|
||||||
int reg_offset;
|
|
||||||
/**
|
/**
|
||||||
* Offset in bytes from the start of the register. Values up to a
|
* Offset in bytes from the start of the register. Values up to a
|
||||||
* backend_reg::reg_offset unit are valid.
|
* backend_reg::reg_offset unit are valid.
|
||||||
*/
|
*/
|
||||||
int subreg_offset;
|
int subreg_offset;
|
||||||
|
|
||||||
struct brw_reg fixed_hw_reg;
|
|
||||||
|
|
||||||
fs_reg *reladdr;
|
fs_reg *reladdr;
|
||||||
|
|
||||||
bool negate;
|
|
||||||
bool abs;
|
|
||||||
|
|
||||||
/** Register region horizontal stride */
|
/** Register region horizontal stride */
|
||||||
uint8_t stride;
|
uint8_t stride;
|
||||||
};
|
};
|
||||||
|
|
|
@ -22,6 +22,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
#include "brw_reg.h"
|
||||||
#include "brw_defines.h"
|
#include "brw_defines.h"
|
||||||
#include "main/compiler.h"
|
#include "main/compiler.h"
|
||||||
#include "glsl/ir.h"
|
#include "glsl/ir.h"
|
||||||
|
@ -39,6 +40,37 @@ enum PACKED register_file {
|
||||||
UNIFORM, /* prog_data->params[reg] */
|
UNIFORM, /* prog_data->params[reg] */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct backend_reg
|
||||||
|
{
|
||||||
|
enum register_file file; /**< Register file: GRF, MRF, IMM. */
|
||||||
|
uint8_t type; /**< Register type: BRW_REGISTER_TYPE_* */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Register number.
|
||||||
|
*
|
||||||
|
* For GRF, it's a virtual register number until register allocation.
|
||||||
|
*
|
||||||
|
* For MRF, it's the hardware register.
|
||||||
|
*/
|
||||||
|
uint16_t reg;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Offset within the virtual register.
|
||||||
|
*
|
||||||
|
* In the scalar backend, this is in units of a float per pixel for pre-
|
||||||
|
* register allocation registers (i.e., one register in SIMD8 mode and two
|
||||||
|
* registers in SIMD16 mode).
|
||||||
|
*
|
||||||
|
* For uniforms, this is in units of 1 float.
|
||||||
|
*/
|
||||||
|
int reg_offset;
|
||||||
|
|
||||||
|
struct brw_reg fixed_hw_reg;
|
||||||
|
|
||||||
|
bool negate;
|
||||||
|
bool abs;
|
||||||
|
};
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
|
|
||||||
class cfg_t;
|
class cfg_t;
|
||||||
|
|
|
@ -91,21 +91,7 @@ class dst_reg;
|
||||||
unsigned
|
unsigned
|
||||||
swizzle_for_size(int size);
|
swizzle_for_size(int size);
|
||||||
|
|
||||||
class reg
|
class src_reg : public backend_reg
|
||||||
{
|
|
||||||
public:
|
|
||||||
/** Register file: GRF, MRF, IMM. */
|
|
||||||
enum register_file file;
|
|
||||||
/** virtual register number. 0 = fixed hw reg */
|
|
||||||
int reg;
|
|
||||||
/** Offset within the virtual register. */
|
|
||||||
int reg_offset;
|
|
||||||
/** Register type. BRW_REGISTER_TYPE_* */
|
|
||||||
int type;
|
|
||||||
struct brw_reg fixed_hw_reg;
|
|
||||||
};
|
|
||||||
|
|
||||||
class src_reg : public reg
|
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
DECLARE_RALLOC_CXX_OPERATORS(src_reg)
|
DECLARE_RALLOC_CXX_OPERATORS(src_reg)
|
||||||
|
@ -129,8 +115,6 @@ public:
|
||||||
explicit src_reg(dst_reg reg);
|
explicit src_reg(dst_reg reg);
|
||||||
|
|
||||||
GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
|
GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
|
||||||
bool negate;
|
|
||||||
bool abs;
|
|
||||||
|
|
||||||
src_reg *reladdr;
|
src_reg *reladdr;
|
||||||
};
|
};
|
||||||
|
@ -174,7 +158,7 @@ negate(src_reg reg)
|
||||||
return reg;
|
return reg;
|
||||||
}
|
}
|
||||||
|
|
||||||
class dst_reg : public reg
|
class dst_reg : public backend_reg
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
|
DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
|
||||||
|
|
|
@ -34,7 +34,7 @@ using namespace brw;
|
||||||
namespace brw {
|
namespace brw {
|
||||||
|
|
||||||
static void
|
static void
|
||||||
assign(unsigned int *reg_hw_locations, reg *reg)
|
assign(unsigned int *reg_hw_locations, backend_reg *reg)
|
||||||
{
|
{
|
||||||
if (reg->file == GRF) {
|
if (reg->file == GRF) {
|
||||||
reg->reg = reg_hw_locations[reg->reg];
|
reg->reg = reg_hw_locations[reg->reg];
|
||||||
|
|
Loading…
Reference in New Issue